AI: Deeper Learning with Intel® Omni-Path Architecture

September 18, 2017

Deep learning is a powerful tool that identifies patterns, extracts meaning from large, diverse datasets, and solves complex problems.  However, integrating neural networks into existing compute environments is a challenge that often requires specialized and costly infrastructure.

New software and hardware options will simplify the complexity.

  • Figure 1. A 32-node cluster based on Intel® Xeon Phi™ processors and Intel® Omni-Path Architecture demonstrated near-linear scaling running a neural network training workload based on Google TensorFlow.
    Figure 1. A 32-node cluster based on Intel® Xeon Phi™ processors and Intel® Omni-Path Architecture demonstrated near-linear scaling running a neural network training workload based on Google TensorFlow.

    Intel® Omni-Path Architecture (Intel® OPA) is well suited to the demands of deep learning, enabling near-linear scalability across large numbers of nodes to provide fast time to results for large problems (see Figure 1).

  • Intel® Xeon® Scalable processors provide up to 2.2X higher neural network training performance than previous-generation Intel Xeon processors.[i]
  • Intel® Xeon Phi™ processors provide extreme parallelism, and deliver up to a teraflop or more of performance for neural network training, without the inherent latencies of GPUs or other PCIe-connected devices.
  • Intel optimized tools, libraries, and frameworks for deep learning provide better performance on Intel architecture than non-optimized software.

A key focus of deep learning implementations is to reduce the time to train the model and to ensure a high level of accuracy. HPC clusters provide a scalable foundation for addressing this need.[ii] However, due to workload characteristics and the compute capabilities of Intel Xeon processors, a high speed, low latency network fabric interconnect is needed to reduce the chance of a performance bottleneck. The fabric must allow all nodes to communicate quickly and effectively, so the servers don’t waste valuable compute cycles waiting to send and receive information.

As part of Intel® Scalable System Framework (Intel® SSF), Intel OPA is designed to tackle the compute- and data-intensive workloads of deep learning and other HPC applications. This high-speed fabric is developed in tandem with Intel compute and storage technologies. The resulting integration helps to resolve many of the performance and cost challenges associated with traditional HPC fabrics.

A Fabric for the Future of AI—and Other HPC Workloads

Deep learning frameworks differ, but the general workflow is the same as it is for many other HPC applications: work the calculation, iterate, then blast out the results to adjacent workloads. During the data sharing stage, a high volume of very small, latency-sensitive messages is broadcast across the fabric.

Breaking Down Barriers in AI

As the interconnect for the Pittsburgh Supercomputing Center’s supercomputer, known as Bridges, Intel® Omni-Path Architecture (Intel® OPA) is already helping to push the boundaries of AI. Bridges compute resources were used to train and run Libratus, an AI application that beat four of the world’s top poker players in a no-limit, Texas Hold ‘em tournament.

The performance and scale of Bridges enabled Libratus to refine its strategy each night based on the previous day’s play. One player said it felt like he was “playing against someone who could see his cards.”

The victory was about more than bragging rights. Libratus is applicable to other two-player zero-sum games, such as cyber-security, adversarial negotiations, and military planning, so beating humans has profound implications.

Read more about the Bridges supercomputer and Intel OPA.

Intel OPA transmits this traffic with the same 100 Gbps line speed as other high-speed fabrics, but this tells only part of the story. It also includes optimizations that address common bottlenecks.

  • Low-Latency, Even at Extreme Scale. Intel OPA provides traffic shaping and quality of service features to improve data flow and prioritize MPI traffic. These advantages help to reduce latency by up to 11 percent versus EDR InfiniBand, with up to 64 percent higher messaging rates.[i]
  • Better Price Performance. Intel OPA is based on a 48-port chip architecture (versus 36-port for InfiniBand). This reduces the number of switches, cables, and switch hops in medium to large clusters, which provides both cost and performance advantages.
  • Improved Accuracy and Resilience. Unlike InfiniBand, Intel OPA implements no-latency error checking, which improves data accuracy without slowing performance. It also stays up and running in the event of a physical link failure, so applications can run to completion, a crucial advantage for lengthy training runs.

Tight Integration Throughout the Stack

Tight integration among Intel OPA and the other components defined by Intel SSF provides additional value. For example, Intel Xeon Scalable processors and Intel Xeon Phi processors are available with integrated Intel OPA controllers to reduce the cost associated with separate fabric cards.

Intel also developed and tested Intel OPA in combination with our full HPC software stack, including Intel® HPC Orchestrator, Intel® MPI, the Intel® Math Kernel Library for Deep Neural Networks (Intel® MKL-DNN), and the Intel® Machine Learning Scaling Library (Intel® MLSL). This integration helps to improve performance and reliability. It also reduces the complexity of designing, deploying, and managing an HPC cluster.

Figure 2. The Intel® Scalable System Framework simplifies the design of efficient, high-performing clusters that optimize the value of HPC investments.

A Faster Road to Pervasive Intelligence

Learn more about Intel SSF benefits for AI and other HPC workloads at each level of the solution stack: compute, memory, storage, fabric, and software.AI is still in its infancy. Tomorrow’s neural networks will dwarf those of today. The mission of Intel OPA and the full Intel SSF solution stack is to make the computing foundation for this growth as simple, scalable and affordable as possible, not only for AI, but for all HPC workloads. This will help to ensure that front-line innovators have the tools they need to support their core mission—transforming the world through deep, pervasive intelligence.

[1] For details, see https://www.intel.com/content/www/us/en/processors/xeon/scalable/xeon-scalable-platform.html

[2] Not all deep learning frameworks are optimized to run efficiently on HPC clusters. Intel is working with the vendor and open source communities to resolve this issue and to lay the foundation for increasingly large neural networks acting on petabyte-scale datasets.

[3] For details, see https://www.intel.com/content/www/us/en/high-performance-computing-fabrics/omni-path-architecture-performance-overview.html

 

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Researchers Scale COSMO Climate Code to 4888 GPUs on Piz Daint

October 17, 2017

Effective global climate simulation, sorely needed to anticipate and cope with global warming, has long been computationally challenging. Two of the major obstacles are the needed resolution and prolonged time to compute Read more…

By John Russell

UCSD Web-based Tool Tracking CA Wildfires Generates 1.5M Views

October 16, 2017

Tracking the wildfires raging in northern CA is an unpleasant but necessary part of guiding efforts to fight the fires and safely evacuate affected residents. One such tool – Firemap – is a web-based tool developed b Read more…

By John Russell

Exascale Imperative: New Movie from HPE Makes a Compelling Case

October 13, 2017

Why is pursuing exascale computing so important? In a new video – Hewlett Packard Enterprise: Eighteen Zeros – four HPE executives, a prominent national lab HPC researcher, and HPCwire managing editor Tiffany Trader Read more…

By John Russell

HPE Extreme Performance Solutions

“Lunch & Learn” to Explore the Growing Applications of Genomic Analytics

In the digital age of medicine, healthcare providers are rapidly transforming their approach to patient care. Traditional technologies are no longer sufficient to process vast quantities of medical data (including patient histories, treatment plans, diagnostic reports, and more), challenging organizations to invest in a new style of IT to enable faster and higher-quality care. Read more…

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Fujitsu Tapped to Build 37-Petaflops ABCI System for AIST

October 10, 2017

Fujitsu announced today it will build the long-planned AI Bridging Cloud Infrastructure (ABCI) which is set to become the fastest supercomputer system in Japan Read more…

By John Russell

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Debuts Programmable Acceleration Card

October 5, 2017

With a view toward supporting complex, data-intensive applications, such as AI inference, video streaming analytics, database acceleration and genomics, Intel i Read more…

By Doug Black

OLCF’s 200 Petaflops Summit Machine Still Slated for 2018 Start-up

October 3, 2017

The Department of Energy’s planned 200 petaflops Summit computer, which is currently being installed at Oak Ridge Leadership Computing Facility, is on track t Read more…

By John Russell

US Exascale Program – Some Additional Clarity

September 28, 2017

The last time we left the Department of Energy’s exascale computing program in July, things were looking very positive. Both the U.S. House and Senate had pas Read more…

By Alex R. Larzelere

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Leading Solution Providers

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

Intel, NERSC and University Partners Launch New Big Data Center

August 17, 2017

A collaboration between the Department of Energy’s National Energy Research Scientific Computing Center (NERSC), Intel and five Intel Parallel Computing Cente Read more…

By Linda Barney

  • arrow
  • Click Here for More Headlines
  • arrow
Share This