Purdue Researchers Hit DARPA Cooling Target of 1000W/cm^2

By John Russell

October 24, 2017

Cooling is an ongoing challenge in all of computing. Now, a group of researchers from Purdue University have devised an ‘intra-chip’ cooling technique that hits the 1000-watt per square centimeter target singled out by DARPA. The new approach relies of fabricating microchannels in chips and flowing a coolant through them.

Attaching heatsinks to chips has long been the common practice. However new efforts to stack chips on top of each other to increase performance and capacity complicates that approach.

“This presents a cooling challenge because if you have layers of many chips, normally each one of these would have its own system attached on top of it to draw out heat. As soon as you have even two chips stacked on top of each other the bottom one has to operate with significantly less power because it can’t be cooled directly confound that approach,” said Justin Weibel, a research associate professor in Purdue’s School of Mechanical Engineering, and co-investigator on the project.

The work has been funded with a four-year grant issued in 2013 totaling around $2 million from the U.S. Defense Advanced Research Projects Agency and the new findings are detailed in a paper[i] appearing on Oct. 12 in the International Journal of Heat and Mass Transfer. There’s also an article[ii] on the work posted yesterday on the Purdue web site.

Use of small microchannels is the key but doing so also complicates the process. “It’s been known for a long time that the smaller the channel the higher the heat-transfer performance,” said Kevin Drummond, one of the paper’s lead authors and doctoral student. “We are going down to 15 or 10 microns in channel width, which is about 10 times smaller than what is typical for microchannel cooling technologies.”

Although using ultra-small channels increases the cooling performance, it is difficult to pump the required rates of liquid flow through the tiny microchannels. The Purdue team overcame this problem by designing a system of short, parallel channels instead of long channels stretching across the entire length of the chip. A special “hierarchical” manifold distributes the flow of coolant through these channels.

“So, instead of a channel being 5,000 microns in length, we shorten it to 250 microns long,” said Suresh Garimella, PI on the project, “The total length of the channel is the same, but it is now fed in discrete segments, and this prevents major pressure drops. So this represents a different paradigm.” The channels were etched in silicon with a width of about 15 microns but a depth of up to 300 microns.

“I think for the first time we have shown a proof of concept for embedded cooling for Department of Defense and potential commercial applications,” Garimella said. “This transformative approach has great promise for use in radar electronics, as well as in high-performance supercomputers. In this paper, we have demonstrated the technology and the unprecedented performance it provides.”

“This number of 1,000 watts per square centimeter is sort of a Holy Grail of microcooling, and we’ve demonstrated this capability in a functioning system with an electrically insulated liquid,” Garimella said.

Image caption: A new electronics-cooling technique relies on microchannels, just a few microns wide, embedded within the chip itself. The device was built at Purdue University’s Birck Nanotechnology Center. (Purdue University photo/ Kevin P. Drummond)

[i] A hierarchical manifold microchannel heat sink array for high-heat-flux two-phase cooling of electronics, http://www.sciencedirect.com/science/article/pii/S0017931017322573

[ii] Purdue develops ‘intrachip’ micro-cooling system for high-performance radar, supercomputers, http://www.purdue.edu/newsroom/releases/2017/Q4/purdue-develops-intrachip-micro-cooling-system-for-high-performance-radar,-supercomputers—.html

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