When the Chips Are Down

By Dairsie Latimer

January 11, 2018

In the last article (“The High Stakes Semiconductor Game that Drives HPC Diversity”) I alluded to the challenges facing the semiconductor industry and how that may impact the evolution of HPC systems over the next few years. I thought I’d lift the covers a little and look at some of the commercial challenges that impact the component technology we use in HPC.

The semiconductor market has experienced a sustained growth phase over the last twenty years but there have been periods where year on year revenues have collapsed (in particular 2001 and 2009). Despite our almost insatiable appetite for new technology (almost all predicated on semiconductors) the commodity semiconductor industry is as vulnerable to boom and bust as any other market. What triggers one of these cycles is usually down to the confluence of one or more issues around:

• Capital spending and investment patterns
• Process migration challenges
• Change in demand (often due to disruptive technologies)

Like most of forecasting the only truly precise science is done retrospectively. It is notoriously hard to predict when a disruptive technology will really fulfill its full potential as there are usually so many interdependencies which can disturb momentum. Falter for too long and the next ‘big thing’ comes along and the ever fickle market starts investing somewhere else.

Of the main three triggers, capital spending is probably the easiest to track and like unemployment in traditional economics, it is responsible hysteresis in the consumer semiconductor market. In other words, the consequences of an over or under investment in capital spending (for new fabs, process and technology transitions, etc.) means there is an inevitable time lag before the effects can be addressed.

Historically when the semis are profitable and can see strong demand for a product, they invest in additional manufacturing capacity (which takes some time to come online – order of three-plus years for a greenfield site). As this new capacity starts to ramp, depending on how firm the demand for the commodity is, price competition starts to kick in and margins erode. If there is significant oversupply in the market then the price can collapse, with the attendant short term cheer for consumers. However, when this happens it causes a glitch in the capital spending pattern which then drives the cycle again as demand again outstrips supply and prices rise.

Now in the last decade there have been two significant changes to the way the semiconductor market has evolved. The first is the dramatically increasing capital costs for developing lower geometry processes for high capacity foundries. Secondly there has been a steady reduction in the number of companies who can afford to invest the $8B+ per modern fab. That list probably stands at fewer than ten that can really afford to do it without direct state intervention.

That said, the strong growth in demand for semiconductors means current investment levels are at record highs. So will the market experience a bust cycle in the next few years? Probably not just yet, but that certainly doesn’t mean the HPC market is out of the woods.

We’re all aware of the precipitous climb in memory costs for HPC systems in the last twelve months. Why you ask, is this happening in a market where the investment in capacity is at record levels? Well now we come back to the risks attached to relying on commodity and therefore consumer electronics to drive the development process.

The bulk of the commodity DRAM is aimed at the mobile and consumer market, where memory capacity of 4-8 GB is the sweet spot (roughly 0.5 – 1 GB per core). While memory requirements for HPC applications vary significantly, a typical installation aims for 1-2GB per core and for the larger scale installations that is creeping upwards steadily.

What this means is that the volume in the market is biased towards the commodity DDR4 density which simply isn’t designed to deliver 16/32/64 GB per DIMM (lets ignore the insanity of 128 GB DRAM DIMMS for now). This goes back to my original thesis, which is that much of HPCs ‘free lunch’ (thanks Herb) is over and we will return to value rather than purely commodity driven pricing.

We have a not dissimilar pattern emerging from the NAND market, where 3D NAND has apparently ridden to the rescue for NAND scaling. Sadly it’s not just capacity that HPC wants but the low latency and endurance. This is different from what the hyperscalers and mobile device vendors typically want which is capacity and low cost.

It also exposes one of the major problems associated with the shift to lower process geometries, deep 3D structures, chip-stacking and complex packaging for ASICs, which is that around 30 percent of the cost of a device is now in the assembly and functional testing portion of the supply and value chain. It adds no intrinsic value but without it you may just have a pile of very expensive sand.

Deep 3D integration also has its own problems, predominantly the sheer number of process steps required for a 48, 64 or 96 string NAND device, which all add complexity and more importantly cost to the supply chain. This means that the cost per bit is not declining as fast as many hoped and according to recent reports it means that NAND will not become price comparable with HDDs for bulk storage for most of the next decade. We’ll ignore for now, just how much more investment would be required to actually deliver the same total capacity to the market that HDDs can for another day.

The issues around process migration have been well documented, as has the parlous state of Moore’s law, the slow ramp of EUV and 450 mm wafers as cost reduction tools and the lack of a clear process path past 7 nm. The semiconductor industry has surpassed even Harry Houdini’s talent of getting out of sticky situations but it is arguably facing its greatest test yet in continuing to innovate and also meet consumer expectations for a continued increase in capacity and capability while also pretending that some things aren’t going to get more difficult and as a result more expensive.

This has profound implications for the HPC market. We’ve long ago accepted that we couldn’t rely on Moore’s law for CPUs to get us to exascale (at least in under 20 MW), for all of the reasons outlined above and many more that are related. So where does that leave us?

Well in the immediate term it leaves us with higher DRAM prices for the next year at least, possibly more until some new fab capacity arrives. Better hope that consumer devices double or better yet quadruple their typical DRAM load out, as that would start to shift the DRAMurai’s focus to higher density memory devices. This would somewhat ease the current situation for HPC which is certainly seeing the effects of higher DRAM prices.

Of course, since we’re already looking at major changes to the memory hierarchy with the introduction of NVDIMMs (NAND or 3DXPoint) this may not turn out to be such a problem. That said NAND prices also rose significantly in 2017, though there is some hope that supply will start to pick up later in 2018 now that the transition to 3D NAND is well under way for most suppliers.

We’ve covered the fact that there is now some real choice in the HPC CPU space and this will certainly help mitigate the spiraling component costs for other aspects of HPC systems but inevitably much of this will eventually be passed on to the customer. Couple that with a rather difficult childhood for the 10 nm process node and the expectation that the transition to 7 nm will be just as challenging, then we’re looking at a period of real pricing uncertainty.
Add in the uncertainties around the latest round of security exploits made public in the last few days and the CPU vendors are going to have to do some hard thinking.

As an industry we should also do some collective soul searching. Do we really care about performance almost to the exclusion of all other imperatives? Or are we now sufficiently concerned about the implications for ‘Meltdown’ and ‘Spectre’ that we pay a bit more than lip-service to the mantra that security is important. The fact is that security isn’t sexy. Most of us don’t get excited about architectural approaches to security and especially not if we’re told that there is a performance penalty. Are we willing to pay the price, especially in time, taken to fix these issues and protect against other similar escapes?

Remember what I said about change in demand?

As we are constantly assured by those promoting Brexit in the UK “Where there’s uncertainty there is opportunity.” So it will be interesting to see how the CPU vendors respond. It will be even more interesting to see how we as consumers change our buying decisions based on what we learn over the next few months.

The changes that will inevitably be needed to address these sorts of vulnerabilities will create other opportunities and I imagine open up the field a little more than we expected even a few weeks ago.

About the Author

Dairsie Latimer has an impeccable and diverse career in IT, having worked in a variety of roles on supplier side and client side across the commercial and public sectors as a consultant and software engineer. Following an early career in computer graphics, micro-architecture design and full stack software development, he has over twelve years’ specialist experience in the HPC sector, ranging from developing low-level libraries and software for novel computing architectures to porting complex HPC applications to a range of accelerators.

As Managing Consultant at Red Oak Consulting, Dairsie advises clients on strategy, technology futures, HPC procurements and managing challenging technical projects. For more information, visit www.redoakconsulting.co.uk.

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