Dealing with HPC Correctness: Challenges and Opportunities

By Ignacio Laguna, Lawrence Livermore National Laboratory and Ganesh Gopalakrishnan, University of Utah

January 25, 2018

Editor’s Note: HPC Correctness – producing reliable HPC code – is a long-term challenge that’s grown only more difficult with the proliferation of heterogeneous computing and the drive towards exascale. This article by Ignacio Laguna (Lawrence Livermore National Laboratory) and Ganesh Gopalakrishnan (University of Utah) describes the problem and reviews recent efforts to develop solutions. As noted in the article, the report from the DOE HPC Correctness Summit has many valuables insights. Thanks also to Sonia Sachs, ALCF Program Manager, Advanced Scientific Computing Research, DOE, who coordinated preparation of the article.

Developing correct and reliable HPC software is notoriously difficult. While effective correctness techniques for serial codes (e.g., verification, debugging and systematic testing) have been in vogue for decades, such techniques are in their infancy for HPC codes. Why is that?

HPC correctness techniques are burdened with all the well-known problems associated with serial software plus special challenges:

  • growing heterogeneity (e.g., architectures with CPUs, special purpose accelerators)
  • massive scales of computation (i.e., some bugs only manifest under very high degrees of concurrency)
  • use of combined parallel programming models (e.g., MPI+X) that often lead to non-intuitive behaviors
  • new scalable numerical algorithms (e.g., to leverage reduced precision in floating-point arithmetic)
  • use of different compilers and optimizations

 

HPC practitioners see additional demands on their time as they learn how to effectively utilize newer machine types that can support much larger problem scales. Developing new and scalable algorithms that work well on next-generation machines while also supporting new science imposes additional—and non-trivial—demands. Developers often don’t have time left to graduate beyond the use of printf debugging or traditional debuggers. Unfortunately, mounting evidence suggests that significant productivity losses due to show-stopper bugs do periodically occur, making the development of better debugging methods inevitable.

Two recent efforts took aim at these challenges. First, an HPC correctness summit sponsored by the U.S. Department of Energy (DOE) resulted in a report (50+ pages) covering a spectrum of issues that can help lay this missing foundation in HPC debugging and correctness.

Second, a well-attended workshop entitled Correctness 2017: First International Workshop on Software Correctness for HPC Applications took place at SC17. This article summarizes these two efforts and concludes with avenues for furthering HPC correctness research. We also invite reader comments on ideas and opportunities to advance this cause.

1. HPC Correctness Summit

Held on January 25–26, 2017, at the DOE headquarters (Washington, D.C.), the HPC Correctness Summit included discussions of several show-stopper bugs that have occurred during large-scale, high-stakes HPC projects. Each bug took several painstaking months of debugging to rectify, revealing the potential for productivity losses and uncertainties of much more severe proportions awaiting the exascale era.

The DOE report distills many valuable nuggets of information not easily found elsewhere. For instance, it compiles one of the most comprehensive tables capturing existing debugging and testing solutions, the family of techniques they fall under, and further details of the state of development of these tools.

The report concludes that we must aim for rigorous specifications, go after debugging automation by emphasizing bug-hunting over formal proofs, and launch a variety of activities that address the many facets of correctness.

These facets include reliable compilation; detecting data races; root-causing the sources of floating-point result variability brought in by different algorithms, compilers, and platforms; combined uses of static and dynamic analysis; focus on libraries; and smart IDEs.

Last but not least, the DOE report laments a near-total absence of a community culture of sharing bug repositories, developing common debugging solutions, and even talking openly about bugs (and not merely about performance and scalability successes). Dr. Leslie Lamport, the 2014 ACM Turing Award Winner, observes that the difficulty of verification can be an indirect measure of how ill-structured the software design is. A famous verification researcher, Dr. Ken McMillan, states it even more directly: We design through debugging. Promoting this culture of openness calls for incentives through well-targeted research grants, as it takes real work to reach a higher plane of rigor. While some of the best creations in the HPC-land were acts of altruism, experience suggests that more than altruism is often inevitable.

Recommendation for sponsoring the Summit was made by the DOE ASCR program manager Dr. Sonia R. Sachs, under the leadership of research director Dr. William Harrod. In addition to the authors of this article, participating researchers were Paul Hovland (Argonne National Lab), Costin Iancu (Lawrence Berkeley National Lab), Sriram Krishnamoorthy (Pacific Northwest National Lab), Richard Lethin (Reservoir Labs), Koushik Sen (UC Berkeley), Stephen Siegel (University of Delaware), and Armando SolarLezama (MIT).

2. HPC Correctness Workshop

As correctness becomes an increasingly important aspect of HPC applications, the research and practitioner community begins to discuss ways to address the problem. Correctness 2017: The First International Workshop on Software Correctness for HPC Applications debuted at the SC conference series on November 12, 2017, demonstrating growing interest on this topic. The goal was to discuss ideas for HPC correctness, including novel research methods to solve challenging problems as well as tools and techniques that can be used in practice today.

A keynote address by Stephen Siegel (Associate Professor, University of Delaware) on the CIVL verification language opened the workshop, followed by seven paper presentations grouped into three categories: applications and algorithms correctness; runtime systems correctness; and code generation and code equivalence correctness.

Topics of discussion included static analysis for finding the root-cause of floating-point variability, how HPC communities like climate modeling deal with platform-dependent result variability, and ambitious proposals aimed at in situ model checking of MPI applications. Participants also examined automated synthesis of HPC algorithms and successes in detecting extremely tricky cases of OpenMP errors by applying rigorous model-level analysis.

While using formal methods to verify large HPC applications is perhaps too ambitious today, a question arose: Can formal methods be applied to verify properties of small HPC programs? (For example, small programs like DOE proxy applications extracted from large production applications could be used to mimic some features of large-scale applications.) Workshop participants agreed that this may be a possibility—at least for some small proxy applications or for some of their key components.

The audience voiced enthusiastic support for continuing correctness workshops at SC. This inaugural workshop was organized by Ignacio Laguna (Lawrence Livermore National Laboratory) and Cindy Rubio-González (University of California at Davis).

3. What’s Next?

As the community depends on in silico experiments for large-scale science and engineering projects, trustworthy platforms and tools will ensure that investments in HPC infrastructures and trained personnel are effective and efficient. While further experience is yet to be gained on cutting-edge exascale machines and their productive use, waiting for the machines to be fully operational before developing effective debugging solutions is extremely short-sighted. Today’s petaflop machines can—and should—be harnessed for testing and calibrating debugging solutions for the exascale era.

Initiatives to address the correctness problem in HPC, such as the DOE summit and the SC17 workshop, are only the beginning of many more such studies and events to follow. In addition to the DOE, the authors thank their own organizations for their support and for facilitating these discussions.

Overall, we encourage the HPC community to acknowledge that debugging is fundamentally an enabler of performance optimizations. While this question was not settled in any formal way at the Correctness workshop, the level of interest exhibited by the attendees coupled with their keen participation suggested that research on rigorous methods at all levels must be encouraged and funded. There was however widespread agreement that conventional methods aren’t bringing in the requisite levels of incisiveness with respect to defect elimination in HPC.

Ganesh Gopalakrishnan’s work is supported by research grants from divisions under the NSF directorate for Computer and Information Science and Engineering. Ignacio Laguna’s work was performed under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under contract DEAC52-07NA27344 (LLNL-MI-744729).

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