Google Charts Two-Dimensional Quantum Course

By Tiffany Trader

April 26, 2018

Quantum error correction, essential for achieving universal fault-tolerant quantum computation, is one of the main challenges of the quantum computing field and it’s top of mind for Google’s John Martinis. Delivering a presentation last week at the HPC User Forum in Tucson, Martinis, one of the world’s foremost experts in quantum computing, emphasized that building a useful quantum device is not just about the number of qubits; getting to 50 or 1,000 or 1,000,000 qubits doesn’t mean anything without quality error-corrected qubits to start with.

Martinis compares focusing on merely the number of qubits to wanting to buy a high-performance computer and only specifying the number of cores. How to create quality qubits is something that the leaders in the quantum space at this nascent stage are still figuring out. Google — as well as IBM, Intel, Rigetti, and Yale – are advancing the superconducting qubit approach to quantum computing. Microsoft, Delft, and UC Santa Barbara are involved in topological quantum computing. Photonic quantum computing and trapped ions are other approaches.

The reason quality is difficult in the first place is that qubits – the processing unit of the quantum system – are fundamentally sensitive to small errors, much more so than the classical bit. Martinis explains with a coin on the table analogy:

“If you want to think about classical bits – you can think of that as a coin on a table; we can represent classical information as heads or tails. Classical information is inherently stable. You have this coin on the table, there’s a restoring force, there’s dissipation so even if there’s a little bit of noise it’s going to be stable at zero or one. In a quantum computer you can represent [a quantum bit] not as a coin on a table but a coin in free space, where say zero is up, and one is down and rotated 90 degrees is zero plus one; and in fact you can have any amount of zero and one and it can rotate in this way to change something called quantum phase. You see since it’s kind of an analog system, it can point in any direction. This means that any small change in this is going to give you an error.

“Error correction in quantum systems is a little bit similar to what you see in classical systems where you have clocked logic so you have a memory source, where you have a clock and every clock period you can compute through some arithmetic logic and then you sequence through this and the clock timing kind of takes care of all the different delays you have in the logic. Similar here, you have kind of repetition of the error correction, based on taking the qubit and encoding it in many other qubits and doing parity measurements to see if you’re having both bit-flip errors going like this or phase flip errors going like that.”

The important thing to remember says Martinis is that if you want to have small errors, exponentially small errors, of 10-9 or 10-12, you need a lot of qubits, i.e., quantity, and pretty low error rates of about one error in one-thousand operations, i.e., quality.

In Martinis’s view, quantum computing is “a two-dimensional horse race,” where the tension between quality and quantity means you can’t think in terms of either/or; you have to think about doing both of them at the same time. Progress of the field can thus be charted on a two-dimensional plot.

The first thing to note when assessing the progress in the field are the limiting error rate and the number of qubits for a single device, says Martinis. The chart depicts, for a single device, the worst error rate, the limiting error rate, and the number of qubits. Google is aiming for an error correction of 10-3 in about 103 qubits.

“What happens, “says Martinis, “is as that error rate goes up the number of qubits you have to have to do error correction properly goes up and blows up at the error correction threshold of about 1 percent. I call this the error correction gain. It’s like building transistors with gain; if you want to make something useful you have to have an error correction that’s low enough. If the error correction is not good enough, it doesn’t matter if you have a billion qubits, you are never going to be able to make them more accurate.”

Up to 50 qubits is classically simulatable, but if the error rate is high it gets easier but it is not useful. Pointing to the lower half of the chart, Martinis says “we want to be down here and making lots of qubits. It’s only once you get down here [below the threshold] that talking quantity by itself makes sense.”

One of the challenges of staying under that error correction threshold is that scaling qubits itself can impede error correction, due to undesired cross-talk between qubits. Martinis says that the UC Santa Barbara technology it is working with was designed to reduce cross-talk to produce a scalable technology. For flux cross-talk, fledgling efforts were at 30-40 percent cross-talk. “The initial UC Santa Barbara device was between 1 percent to .1 percent cross-talk and now it’s 10-5,” says Martinis, adding “we barely can measure it.”

The solid black dot on the chart (above) represents that UC Santa Barbara chip. It is 9 qubits and dips just beneath the error correction threshold. Now with its follow-on Bristlecone chip architecture, Google is working to scale the UCSB prototype to >50 qubits to show quantum supremacy, the point at which it would be longer feasible to classically simulate it. The Google team is focused on improving error correction with the expectation that near-term applications will then be feasible. Martinis says the next step is to move out to ~1,000 qubits with exponentially small errors. The end goal is to scale up to a million-or-so qubits with low error rates to solve real-world problems that are intractable on today’s best supercomputers.

The Bristlecone chip consists of 72 qubits, arranged in 2D array. The device has been made and is now undergoing testing to make sure it is operating correctly. Google uses its Qubit Speckle algorithm to validate its quantum supremacy experiments.

Martinis reports that progress on quantum algorithms is also advancing. One of the most compelling applications for quantum computers is quantum chemistry. It’s a natural application for quantum computing, says Martinis. The algorithm though is exponentially hard. In 2011, Microsoft’s quantum computing group documented an O(n11) quantum chemistry algorithm, which would take the age of the universe to run. Work has since progressed and recently the Google theory group showed an algorithm that is Õ(N2.67) for the exact solution and O(N) for the approximate. “[The exact implementation] would take about 100 logical qubits, requiring a million physical qubits,” Martinis notes. “It’s beyond what we can do now, but now the numbers are reasonable so we can think about doing it.”

In closing, Martinis points out that the metrics for assessing the progress of quantum computing in addition to quality and quantity also include speed and connectivity. In different technologies, there can be a factor of 105 or so different speeds. For networking, he says you need at least 2D nearest neighbor corrections to do the error correction properly. Referring to the chart on Google’s key metrics (at left), Martinis says the company isn’t ready to talk about Bristlecone’s error-correction or speed yet but it anticipates good numbers and hopes to show quantum supremacy “very soon.”

Link to slides: https://www.hpcuserforum.com/presentations/tuscon2018/QCOverview_Google_UFTucson2018.pdf

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

At Long Last, Supercomputing Helps to Map the Poles

August 22, 2019

For years,” Paul Morin wrote, “those of us that made maps of the Poles apologized. We apologized for the blank spaces on maps, we apologized for mountains being in the wrong place... Read more…

By Oliver Peckham

Xilinx Says Its New FPGA is World’s Largest

August 21, 2019

In this age of exploding “technology disaggregation” – in which the Big Bang emanating from the Intel x86 CPU has produced significant advances in CPU chips and a raft of alternative, accelerated architectures... Read more…

By Doug Black

Supercomputers Generate Universes to Illuminate Galactic Formation

August 20, 2019

With advanced imaging and satellite technologies, it’s easier than ever to see a galaxy – but understanding how they form (a process that can take billions of years) is a different story. Now, a team of researchers f Read more…

By Oliver Peckham

AWS Solution Channel

Efficiency and Cost-Optimization for HPC Workloads – AWS Batch and Amazon EC2 Spot Instances

High Performance Computing on AWS leverages the power of cloud computing and the extreme scale it offers to achieve optimal HPC price/performance. With AWS you can right size your services to meet exactly the capacity requirements you need without having to overprovision or compromise capacity. Read more…

HPE Extreme Performance Solutions

Bring the combined power of HPC and AI to your business transformation

FPGA (Field Programmable Gate Array) acceleration cards are not new, as they’ve been commercially available since 1984. Typically, the emphasis around FPGAs has centered on the fact that they’re programmable accelerators, and that they can truly offer workload specific hardware acceleration solutions without requiring custom silicon. Read more…

IBM Accelerated Insights

Keys to Attracting the Newest HPC Talent – Post-Millennials

[Connect with HPC users and learn new skills in the IBM Spectrum LSF User Community.]

For engineers and scientists growing up in the 80s, the current state of HPC makes perfect sense. Read more…

Singularity Moves Up the Container Value Chain

August 20, 2019

The enterprise version of the Singularity HPC container platform released this week by Sylabs is designed to allow users to create, secure and share the high-end containers in self-hosted production deployments. The e Read more…

By George Leopold

At Long Last, Supercomputing Helps to Map the Poles

August 22, 2019

For years,” Paul Morin wrote, “those of us that made maps of the Poles apologized. We apologized for the blank spaces on maps, we apologized for mountains being in the wrong place... Read more…

By Oliver Peckham

IBM Deepens Plunge into Open Source; OpenPOWER to Join Linux Foundation

August 20, 2019

IBM today announced it was contributing the instruction set (ISA) for its Power microprocessor and the designs for the Open Coherent Accelerator Processor Inter Read more…

By John Russell

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a Read more…

By Rob Johnson

AI is the Next Exascale – Rick Stevens on What that Means and Why It’s Important

August 13, 2019

Twelve years ago the Department of Energy (DOE) was just beginning to explore what an exascale computing program might look like and what it might accomplish. Today, DOE is repeating that process for AI, once again starting with science community town halls to gather input and stimulate conversation. The town hall program... Read more…

By Tiffany Trader and John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Lenovo Drives Single-Socket Servers with AMD Epyc Rome CPUs

August 7, 2019

No summer doldrums here. As part of the AMD Epyc Rome launch event in San Francisco today, Lenovo announced two new single-socket servers, the ThinkSystem SR635 Read more…

By Doug Black

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

Cray, AMD to Extend DOE’s Exascale Frontier

May 7, 2019

Cray and AMD are coming back to Oak Ridge National Laboratory to partner on the world’s largest and most expensive supercomputer. The Department of Energy’s Read more…

By Tiffany Trader

Graphene Surprises Again, This Time for Quantum Computing

May 8, 2019

Graphene is fascinating stuff with promise for use in a seeming endless number of applications. This month researchers from the University of Vienna and Institu Read more…

By John Russell

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

A Behind-the-Scenes Look at the Hardware That Powered the Black Hole Image

June 24, 2019

Two months ago, the first-ever image of a black hole took the internet by storm. A team of scientists took years to produce and verify the striking image – an Read more…

By Oliver Peckham

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

Chinese Company Sugon Placed on US ‘Entity List’ After Strong Showing at International Supercomputing Conference

June 26, 2019

After more than a decade of advancing its supercomputing prowess, operating the world’s most powerful supercomputer from June 2013 to June 2018, China is keep Read more…

By Tiffany Trader

In Wake of Nvidia-Mellanox: Xilinx to Acquire Solarflare

April 25, 2019

With echoes of Nvidia’s recent acquisition of Mellanox, FPGA maker Xilinx has announced a definitive agreement to acquire Solarflare Communications, provider Read more…

By Doug Black

Qualcomm Invests in RISC-V Startup SiFive

June 7, 2019

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups. Last fall, Esperanto Technologies announced a $58 million funding round. Read more…

By George Leopold

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This