No Go for GloFo at 7nm; and the Fujitsu A64FX post-K CPU

By Dairsie Latimer

September 5, 2018

It’s been a news worthy couple of weeks in the semiconductor and HPC industry. There were several HPC relevant disclosures at Hot Chips 2018 to whet appetites. This included details of the newest entrant to the HPC processor space, Fujitsu’s A64FX. However, more far reaching news came last week as Global Foundries announced it has decided to put its 7 nm node on hold, and entirely stopped development of nodes beyond 7 nm. This has some clear ramifications for the HPC industry.

Three green bottles

With Global Foundries shuttering development there are now only three companies left in the game at 10/7 nm; TSMC, Samsung and Intel. Of these, two are already significantly delayed reaching volume manufacturing with their current next generation process. TSMC were already in pole position at 7 nm, with numerous designs already taped out and sampling, and now it would seem that they are effectively the only game in town for now. As a result, in a year or two we may even notice some signs of supply constraints if TSMC’s 7 nm customers saturate their production capacity.

What’s behind the Global Foundries’ decision?

Put simply it’s one of simple demand economics. Non-recurring engineering costs at lower process nodes (including 10 and 7 nm) are spiralling, with some industry analysts suggesting that they are now approaching $200 million if one factors in all of the costs to reach volume manufacturing.

This will limit the number of customers actually wanting to or indeed able to afford to use the lower geometry nodes for mass market manufacturing and that previous nodes will be longer lived. As Global Foundries really only had AMD and IBM as potential customers at 7 nm it seems that lack of demand at 7 nm for their process (compared to TSMC’s) is the real driver behind this decision.

Despite the initial DNA of Global Foundries, the relationship with AMD has blown hot and cold for years. Once AMD clearly signalled their manufacturing intentions for next generation 7 nm silicon (Rome) was at TSCM, this meant that Global Foundries’ lead customer at 7 nm had effectively disappeared. No sense in making a further $2-4 billion investment in a fab that would never reach anything approaching the production levels necessary to pay for it.

It also leaves IBM in a potentially difficult position as Global Foundries are one of their process technology partners (having sold their foundry business to them some while back). It’s too soon for any public disclosure how this will impact IBM’s Power roadmap (which was linked with 10 nm for Power10 but which Global Foundries skipped to concentrate on 7 nm.) All this could mean a disruptive realignment for their ASIC teams if they are to move to Samsung (who are part of a research alliance comprising IBM, Global Foundries and Samsung) or TSMC for manufacturing 10/7 nm.

The Global Foundries CEO noted that projections for 2022 are almost two thirds of volume manufacturing will still be on 12 nm and above and so older nodes will be profitable for a good while yet. Global Foundries also has some interesting opportunities with their FD-SOI processes in the growing extreme mobile and RF markets, where absolute power efficiency is more important than transistor density driving Moore’s law.

Is this really the end of the road for silicon scaling?

We’ve seen for the last four or five years bulk CMOS silicon scaling (and Moore’s law) is stalling (arguably from the 22/14 nm transition). We’ve seen another major inflection point at the 10/7 nm transition and while there is a tentative roadmap to sub 5 nm (or even 2 nm) it’s based on optimistic projections for EUV availability and innovations in transistor design that have proven elusive thus far.

More worryingly the traditional separation of concerns between architecture design and backend (place and route of synthesised designs) is becoming blurred as even the increasingly restrictive design rules struggle to ensure viable designs for volume manufacture.

There are an increasing number of effects that process engineers, as well as standard cell designers, need to track and solve for, many of which can translate to significant yield variations even from wafer to wafer, let alone process generation to process generation and foundry to foundry.

Process variations of up to 10 percent may now actually take away much of the full advantage of using a new process node, unless the standard cell providers and EDA vendors can provide easily utilised enhancements to their logic libraries and place and route techniques. Now more than ever there needs to be a tight coupling between the customer, the foundry and EDA tool vendor to ensure that performance and yields are kept at economically viable levels.

Developments in transistor design, especially around the use of variable pitch nanosheets (which has very some attractive properties) rather than the increasingly difficult to manufacture finFETs, may well mean that there is still some limited density scaling benefit to moving to lower geometry nodes, but at a greatly reduced rate compared to the heyday of Moore’s law.

It’s more than likely that the curve that describes the actual cost per transistor, which has declined over time, has done more than flatten out recently and we may well see a further reverse in real terms. Couple this with the spiralling investments required to continue lithography scaling (for both foundry and customer) and the rapidly dwindling number of companies able to do so it’s clear that we are actually witnessing the last major inflection point for Moore’s law as it is currently constituted.

If costs per transistor no longer decrease as a result of minimal area scaling on lower geometry nodes then other means of transistor density scaling at a package level will need to be adopted. This will lead to an increasing focus on die stacking, monolithic 3D fabrication and multi-chip-modules, as well as potentially increased integration of on package communications links. Expect to see solutions utilising these techniques proliferate in HPC in the next few years.

Fujitsu’s A64FX

All of which neatly brings us onto one of the most interesting announcements at Hot Chips 30 and probably by far the most anticipated, which was the public unveiling of key details for the Fujitsu A64FX post-K CPU architecture.

The A64FX is made up of a relatively modest 8.7 billion transistors and is baked on a 7 nm process node. No official details of who’s but it don’t take much of a genius to work it out. It’s the first CPU to implement Arm’s Scalable Vector Extensions (SVE), specifically intended for high performance computing (and AI workloads) as well as a host of other interesting system level features.

In many respects it represents an ARM flavoured version of the tried and tested recipe followed by Fujitsu for the K Computer (and the later Sparc64-XIfx), but with a few notable enhancements. Prof. Satoshi Matsuoka also noted (on Twitter) that the TDP for the A64FX was likely to be eye catching (in a good way). Given the high level of integration it will be interesting to see how they do here but I expect they’re hoping to hit around the 160-180W mark. Working back from the quoted peak DP TFlops of 2.7, this implies a relatively modest 1.75GHz clock speed which will help. Then again if you are hoping to be able to scale to 200-300k nodes (and 384 nodes in a 48U rack) a power sipping TDP is pretty much a prerequisite.

Other notable metrics include 1TB/s memory bandwidth delivered by four 8GB stacks of HBM2 memory (rather than the HMC on the prior Sparc64-XIfx), each one associated with a Core Memory Group of cores (12 compute + 1 helper on a crossbar) all connected via coherent caches to the system ring bus and the Tofu3 port. The Tofu3 fabric supplies the main off chip connectivity (the PCIe3 is there for peripherals) and is currently a modest upgrade from the Tofu2 interconnect on the Sparc64-XIfx.

One interesting aspect to consider is the amount of memory per core (assuming 1GB pinned per helper core) which is around 0.6GB. For many simulation environments (where bandwidth rather than working set size is king) this may not prove a huge handicap but there are workloads which will definitely fall out of node on the ‘current’ A64FX memory configs.

The upshot is that Fujitsu clearly believe that this is well balanced system, compared to some other precursor HPC CPUs that bare some striking similarities. Expectation is that the A64FX may make it to market in 2019, prior to deployment in the post-K machine in 2021. It also perhaps leaves a tantalising glimpse of further possible refinements over the next couple of years before the post-K system is due to be delivered. I wouldn’t be surprised to see some more cores enabled per CMG, along with less probable enhancements to the HMB memory interfaces (faster as well as larger) as well as to the Tofu3 PHYs (more bandwidth if not necessarily lower latency).

Roll on 2019 and beyond.

About the Author

Dairsie Latimer, Technical Advisor at Red Oak Consulting, has a somewhat eclectic background, having worked in a variety of roles on supplier side and client side across the commercial and public sectors as an consultant and software engineer. Following an early career in computer graphics, micro-architecture design and full stack software development, he has over twelve years’ specialist experience in the HPC sector, ranging from developing low-level libraries and software for novel computing architectures to porting complex HPC applications to a range of accelerators. Dairise joined Red Oak Consulting (@redoakHPC) in 2010 bringing his wealth of experience to both the business and customers.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Migration Tools Needed to Shift ML to Production

September 20, 2018

The confluence of accelerators like cloud GPUs along with the ability to handle data-rich HPC workloads will help push more machine learning projects into production, concludes a new study that also stresses the importan Read more…

By George Leopold

Kyoto University ACCMS Implements Fine-grained Power Management

September 19, 2018

Data center power management is a ubiquitous challenge and in few places is it more so than at Kyoto University Academic Center for Computing and Media Studies (ACCMS)) where power consumption limits were imposed followi Read more…

By Staff

What’s New in HPC Research: September (Part 1)

September 18, 2018

In this new bimonthly feature, HPCwire will highlight newly published research in the high-performance computing community and related domains. From exascale to quantum computing, the details are here. Check back every Read more…

By Oliver Peckham

HPE Extreme Performance Solutions

Introducing the First Integrated System Management Software for HPC Clusters from HPE

How do you manage your complex, growing cluster environments? Answer that big challenge with the new HPC cluster management solution: HPE Performance Cluster Manager. Read more…

IBM Accelerated Insights

A Crystal Ball for HPC

People are notoriously bad at predicting the future.  This very much includes experts. In the Forbes article “Why Most Predictions Are So Bad” Philip Tetlock discusses the largest and best-known test of the accuracy of expert predictions which show that any experts would do better if they make random guesses. Read more…

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and development. Among other things it would establish a National Quantu Read more…

By John Russell

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

Nvidia Accelerates AI Inference in the Datacenter with T4 GPU

September 14, 2018

Nvidia is upping its game for AI inference in the datacenter with a new platform consisting of an inference accelerator chip--the new Turing-based Tesla T4 GPU- Read more…

By George Leopold

DeepSense Combines HPC and AI to Bolster Canada’s Ocean Economy

September 13, 2018

We often hear scientists say that we know less than 10 percent of the life of the oceans. This week, IBM and a group of Canadian industry and government partner Read more…

By Tiffany Trader

Rigetti (and Others) Pursuit of Quantum Advantage

September 11, 2018

Remember ‘quantum supremacy’, the much-touted but little-loved idea that the age of quantum computing would be signaled when quantum computers could tackle Read more…

By John Russell

How FPGAs Accelerate Financial Services Workloads

September 11, 2018

While FSI companies are unlikely, for competitive reasons, to disclose their FPGA strategies, James Reinders offers insights into the case for FPGAs as accelerators for FSI by discussing performance, power, size, latency, jitter and inline processing. Read more…

By James Reinders

Update from Gregory Kurtzer on Singularity’s Push into FS and the Enterprise

September 11, 2018

Container technology is hardly new but it has undergone rapid evolution in the HPC space in recent years to accommodate traditional science workloads and HPC systems requirements. While Docker containers continue to dominate in the enterprise, other variants are becoming important and one alternative with distinctly HPC roots – Singularity – is making an enterprise push targeting advanced scale workload inclusive of HPC. Read more…

By John Russell

At HPC on Wall Street: AI-as-a-Service Accelerates AI Journeys

September 10, 2018

AIaaS – artificial intelligence-as-a-service – is the technology discipline that eases enterprise entry into the mysteries of the AI journey while lowering Read more…

By Doug Black

No Go for GloFo at 7nm; and the Fujitsu A64FX post-K CPU

September 5, 2018

It’s been a news worthy couple of weeks in the semiconductor and HPC industry. There were several HPC relevant disclosures at Hot Chips 2018 to whet appetites Read more…

By Dairsie Latimer

TACC Wins Next NSF-funded Major Supercomputer

July 30, 2018

The Texas Advanced Computing Center (TACC) has won the next NSF-funded big supercomputer beating out rivals including the National Center for Supercomputing Ap Read more…

By John Russell

IBM at Hot Chips: What’s Next for Power

August 23, 2018

With processor, memory and networking technologies all racing to fill in for an ailing Moore’s law, the era of the heterogeneous datacenter is well underway, Read more…

By Tiffany Trader

Requiem for a Phi: Knights Landing Discontinued

July 25, 2018

On Monday, Intel made public its end of life strategy for the Knights Landing "KNL" Phi product set. The announcement makes official what has already been wide Read more…

By Tiffany Trader

CERN Project Sees Orders-of-Magnitude Speedup with AI Approach

August 14, 2018

An award-winning effort at CERN has demonstrated potential to significantly change how the physics based modeling and simulation communities view machine learni Read more…

By Rob Farber

ORNL Summit Supercomputer Is Officially Here

June 8, 2018

Oak Ridge National Laboratory (ORNL) together with IBM and Nvidia celebrated the official unveiling of the Department of Energy (DOE) Summit supercomputer toda Read more…

By Tiffany Trader

New Deep Learning Algorithm Solves Rubik’s Cube

July 25, 2018

Solving (and attempting to solve) Rubik’s Cube has delighted millions of puzzle lovers since 1974 when the cube was invented by Hungarian sculptor and archite Read more…

By John Russell

AMD’s EPYC Road to Redemption in Six Slides

June 21, 2018

A year ago AMD returned to the server market with its EPYC processor line. The earth didn’t tremble but folks took notice. People remember the Opteron fondly Read more…

By John Russell

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

Leading Solution Providers

SC17 Booth Video Tours Playlist

Altair @ SC17


AMD @ SC17


ASRock Rack @ SC17

ASRock Rack



DDN Storage @ SC17

DDN Storage

Huawei @ SC17


IBM @ SC17


IBM Power Systems @ SC17

IBM Power Systems

Intel @ SC17


Lenovo @ SC17


Mellanox Technologies @ SC17

Mellanox Technologies

Microsoft @ SC17


Penguin Computing @ SC17

Penguin Computing

Pure Storage @ SC17

Pure Storage

Supericro @ SC17


Tyan @ SC17


Univa @ SC17


Sandia to Take Delivery of World’s Largest Arm System

June 18, 2018

While the enterprise remains circumspect on prospects for Arm servers in the datacenter, the leadership HPC community is taking a bolder, brighter view of the x86 server CPU alternative. Amongst current and planned Arm HPC installations – i.e., the innovative Mont-Blanc project, led by Bull/Atos, the 'Isambard’ Cray XC50 going into the University of Bristol, and commitments from both Japan and France among others -- HPE is announcing that it will be supply the United States National Nuclear Security Administration (NNSA) with a 2.3 petaflops peak Arm-based system, named Astra. Read more…

By Tiffany Trader

D-Wave Breaks New Ground in Quantum Simulation

July 16, 2018

Last Friday D-Wave scientists and colleagues published work in Science which they say represents the first fulfillment of Richard Feynman’s 1982 notion that Read more…

By John Russell

Intel Pledges First Commercial Nervana Product ‘Spring Crest’ in 2019

May 24, 2018

At its AI developer conference in San Francisco yesterday, Intel embraced a holistic approach to AI and showed off a broad AI portfolio that includes Xeon processors, Movidius technologies, FPGAs and Intel’s Nervana Neural Network Processors (NNPs), based on the technology it acquired in 2016. Read more…

By Tiffany Trader

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

Pattern Computer – Startup Claims Breakthrough in ‘Pattern Discovery’ Technology

May 23, 2018

If it weren’t for the heavy-hitter technology team behind start-up Pattern Computer, which emerged from stealth today in a live-streamed event from San Franci Read more…

By John Russell

TACC’s ‘Frontera’ Supercomputer Expands Horizon for Extreme-Scale Science

August 29, 2018

The National Science Foundation and the Texas Advanced Computing Center announced today that a new system, called Frontera, will overtake Stampede 2 as the fast Read more…

By Tiffany Trader

Intel Announces Cooper Lake, Advances AI Strategy

August 9, 2018

Intel's chief datacenter exec Navin Shenoy kicked off the company's Data-Centric Innovation Summit Wednesday, the day-long program devoted to Intel's datacenter Read more…

By Tiffany Trader

GPUs Power Five of World’s Top Seven Supercomputers

June 25, 2018

The top 10 echelon of the newly minted Top500 list boasts three powerful new systems with one common engine: the Nvidia Volta V100 general-purpose graphics proc Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This