Digging into MLPerf Benchmark Suite to Inform AI Infrastructure Decisions

By John Russell

April 9, 2019

With machine learning and deep learning storming into the datacenter, the new challenge is optimizing infrastructure choices to support diverse ML and DL workflows. How many accelerators do you (really) need? Which interconnect scheme works best? How do various frameworks compare on different compute architectures? When can you choose less expensive CPUs and rely on the GPUs to do the magic? How different are the needs of training versus inferencing?

“There is no one server that does the job perfectly well,” said Ramesh Radhakrishnan, distinguished engineer, Dell EMC, to a packed session[I] at GTC last month. “You see a variety of servers used to execute these kinds of workloads.” Precisely to this point, a flurry of benchmarking tools is emerging to help make sense of ML/DL performance requirements and optimizations. There’s the Deep500 with grand ambitions but still very nascent and aimed mostly at very large scale systems. There are early movers – DeepBench, TF_CNN_Bench, and DAWNBench, for example – with typically narrower strengths and notable shortfalls. More recently, MLPerf has started emerging as popular tool that borrows from those coming before it.

MLPerf, a broader ML/DL benchmarking effort supported by industry and academia, is gaining a foothold at least for assessing training workloads. In his GTC session, Demystifying Deep Learning Infrastructure Choices Using MLPerf Benchmark Suite, Radhakrishnan took the audience on a test drive through MLPerf by presenting performance data from testing on four different systems (1-to-8 GPUs) with differing topologies He also offered comments about the other benchmarks and their contribution to progress so far.

Yes the GPUs profiled are all from Nvidia and the systems from Dell EMC – the occasion was GTC after all – but Radhakrishnan’s even-handed approach made for a solid primer. At HPCwire’s request, Nvidia agreed to make the link to Radhakrishnan’s streamed session public ahead of schedule and in time for inclusion in this article. It’s 44 minutes well-spent for those seeking a MLPerf overview. A few of the session highlights are covered here along with key slides from Radhakrishnan’s session.

Given the sudden rise of ML and DL it is perhaps not surprising that benchmarking tools have started sprouting. Each has value. “[Take] TF_CNN_Bench (TensorFlow convolutional neural network benchmark), for example,” said Radhakrishnan. “It’s very commonly used and people use it for different types of GPUs and it works well but is focused on a single domain, convolutional networks. If you are deploying a translation-based network that’s using RNN (recurrent neural networks), can you take the same observations that you made using a CNN (convolutional neural network) and assume the same thing for your other model? [No], there’s going to be differences. So you want to have a wide coverage on domains.”

DeepBench from Baidu does cover different domains. “It is primarily used for measuring the performance of the core operations that happen in your neural networks. [It has] CNN and RNN coverage [but] if you want to look at system level performance, this is not a tool for that. It doesn’t account for software frameworks, it doesn’t account for distributed training – you need the right set of tools for that,” noted Radhakrishnan.

Enter MLPerf. Early last year, “the folks that introduced DAWNBench from Stanford University worked with Google, Baidu, AMD, Intel and others to come up with MLPerf. This addressed a lot of shortcomings in previous benchmarks. It has coverage of different domains. In terms of metrics it borrows from DAWNBench, which uses execution time to [attain accuracy]. You are using Docker containers and producing all the information needed along with providing data sets so anyone can reproduce these [MLPerf] results,” said Radhakrishnan.

Importantly, emphasized Radhakrishnan, MLPerf has extensive support from industry and universities. At this writing more than 30 companies and roughly ten academic institutions are listed on the MLPerf website. This is key to culling out bias and driving MLPerf’s ability to make fair comparisons between systems or between two different ML/DL elements, according to Radhakrishnan. It also gives the organization “freedom to enable innovation to happen.”

So what is MLPerf? The organization describes it as, “A broad ML benchmark suite for measuring performance of ML software frameworks, ML hardware accelerators, and ML cloud platforms.” The current release, version 0.5, has five different domains: image classification, object detection, language translation, reinforcement learning, and recommendation. The MLPerf metric of choice – speedup – is the amount to time that it takes train a neural net model in these domains to state of the art target accuracy.

You can see the models used for each domain on the slide. Generally they represent state of the art models said Radhakrishnan – ResNet-50 used in image identification, is a deep (50 layer) residual neural network introduced in 2015. RNN GNMT (Google Neural Machine Translation, introduced in 2016) and Transformer (an NLP approach introduced in 2017) are likewise leading edge. One of MLPerf’s goals, said Radhakrishnan, is stay very current.

“It’s a very agile development model. There were actually seven or eight domains initially considered; these five made it [into the spec], but you can definitely see more domains being added and those models being refreshed based on what’s current and state of the art,” he said. “MLPerf is definitely a needed tool today and [we’re] really excited about looking to see how it changes over times and expands and adds domains as. It covers training now but I think they are really close to releasing the inference workload as well.”

The first MLPerf published results were in December. Nvidia, no surprise, trumpeted its strong performance. (See HPCwire article, Nvidia Leads Alpha MLPerf Benchmarking Round.) Radhakrishnan suggested those results didn’t have enough data points to examine some of the questions Dell EMC and colleagues at the University of Texas (College of Engineering) were interested in. His slide deck, which will be available soon, is good way to get a fast overview of the exercise.

“What we did in our work is actually run MLPerf against a wide range of platforms, GPU platforms, starting from a workstation with a single CPU and two GPUs, all the way to [a server with] eight GPUs. We decided to do a whole suite of tests ranging across scaling, comparing different GPU models, and looking at interconnect technologies whether it is PCIe or NVLink to help answer some of those questions,” he said.

Shown below is a kind of summary slide showing system performance based on number of GPUs used. The MLPerf score is how much faster the system executes compared to the MLPerf reference “which in this case is a single P100 instance and that P100 is not very well optimized either,” said Radhakrishnan. The smallest machine, based on Quadro GV100, scored 14.

“The score of 14 means this two-GPU platform ran 14 times faster than one P100.  However you should not make the assumption you are going to see that speed difference between P100s and GV100s every time. What this lets you do is you can actually calculate, because now that your baseline is the same, you can make the assumption that an eight-GPU platform performs four time more efficiently than my two-GPU platform. So you can make assumptions on scale. We are seeing some of the benchmarks scale linearly, so something like SSD (single shot multi-box detector) and other image classifications, get really good speed up going from two-to-four-to-eight GPUs. Some of the other benchmarks, recommendation and translation, don’t see that same efficiency and scale,” he said.

The tasks/features outlined in orange in the slide below are the areas benchmarked by Dell EMC.

“One question which always comes up is which framework should I use. Since there is so much information on Tensorflow from Google and Mxnet from Nvidia, we took those two submissions (from the initial MLPerf 0.20 run) and recreated those runs. We did this on a four-GPU NVLink platform, and plotted accuracy against time. Mxnet actually completed the target accuracy in about 245 min whereas TensorFlow took about 265 minutes. One of the reasons they are so close to each other is they take advantage of the Nvidia cuDNN library. In this case we actually looked at the GPU kernels that were being implemented and found that here were eight kernels called by both of these frameworks, they were exactly the same kernels, and they account for about 40 percent on average, of the execution time,” said Radhakrishnan.

For the purposes of his presentation, Radhakrishnan introduced two hypothetical characters Dave, a data scientist concerned only with performance, and Sally, a datacenter infrastructure manager concerned with cost, efficiency, and satisfying diverse constituencies. He discussed how their needs differ and how MLPerf can inform both.

“I showed Dave these results and he said “are you sure your Mxnet is optimized and running properly because I thought tensor flow was slower?” He was right in one way. Because this part of the submission that was done used TensorFlow version 1.12 [which] introduced XLA compiling. What XLA compiling does is basically does tensor fusion where it takes the graph and optimizes some of the optimized kernels that for your particular infrastructure, right, or your GPUs. So when we ran the same run without XLA compiler enabled, it actually took almost 200 minutes longer. One key takeaway is to make sure you are using the right optimizations, so no matter what you have underneath. If you aren’t taking advantage a compiling or using the right options you are going to leave a lot of performance on the table,” said Radhakrishnan.

One interesting result was the dramatic impact being able to use mixed precision during training. Radhakrishnan’s team looked Tesla V100-PCIe performance when used in precision and mixed precision modes.

“With Volta you get the capability of using mixed precision training. What this means is it uses a technique where it combines half-precision floating point and single-precision in order to improve performance and keep the same accuracy you get in your single precision frame. In addition to memory savings, you are also using dedicated hardware on V100s to do 4×4 matrix multiplies. However, there are some coding changes involved to take advantage of this,” noted Radhakrishnan.

As is shown in the slide below, it is worth the effort. Here improvements of roughly 150 percent to 330 percent were achieved. “A Resnet-50 job on an eight-GPU system that runs in about ten minutes if you take advantage of mixed precision; if you don’t it take advantage of it, [it takes] close to 500 minutes. After I prepared this slide yesterday, Jensen Huang (Nvidia CEO) announced you are getting this with practically just one or two lines change in your code. There’s an API exposed and once you enable that, it does different things you are supposed to do to make sure you still maintain the same accuracy,” said Radhakrishnan.

Radhakrishnan presented results from four different interconnect schemes including use of NVLink with GPUs using SXM2 form factor (permits high clock rate), use of PCIe switches, and PCIe standalone. Radhakrishnan noted the last arrangement (scheme on far right of slide) allows users to take a container “pin it to a CPU and then use a GPU” and that this provides the best CPU-to-GPU bandwidth and that’s useful for some applications though he didn’t specify examples.

“If you look at how machine learning performs across all of these designs. If you look at translation benchmarks you see that improves performance by anywhere from 40-to-50 percent and when you look at it in terms of minutes, that’s 20 minutes and 30 minutes. It is a sizeable improvement when you actually look at the percentage. There’s [also] improvement for MaskRCNN. When it comes image classification, you are seeing that the peer-to-peer capability provided by the PCIe switch makes a difference; you actually get difference between that platform and the two where you cannot do peer-to-peer.

“So system design does matter and as an infrastructure provider you definitely want to make sure to assign the tasks that are doing a lot of GPU-to-GPU communication, to the right platform. If you had a mix of platforms in your datacenter, if you have workloads that are actually doing a lot of peer-to-peer like translation benchmark, you want to make sure they get queued up on your NVLink platforms. For some of the other benchmarks, the differences that you get are not that significant,” said Radhakrishnan 

The bottom line, according to Radhakrishnan, is MLPerf provides a needed tool for assessing infrastructure choices as well as ML choices. “Use the tools to monitor and actually figure out how many GPUs you need [because] throwing as many GPUs as you can at the problem does not result in a linear increase in your performance. There are some workloads in which you can definitely see improvement and there are others where you are better off running at one or two GPUs,” he said.

The same is true for interconnect. “We looked at what NVLink brings to the table. For a two GPU system there are a couple of benchmarks for which NVLink did not make a difference,” he said but noted on larger systems NVLink can be critical when performance is your top priority although even there performance can vary by the model used.

There’s quite a bit more in Radhakrishnan’s presentation, including for example deeper dives into CPU utilization – it turns out TensorFlow is a CPU hog – and GPU utilization. It will be interesting to watch MLPerf’s development and how widely adopted it becomes.

Slide source: GTC2019

Link to Radhakrishnan’s GTC streamed (slides and audio) session: https://on-demand.gputechconf.com/gtc/2019/video/_/s9553-demystifying-deep-learning-infrastructure-choices-using-mlperf-benchmark-suite/

[i]Demystifying Deep Learning Infrastructure Choices Using MLPerf Benchmark Suite

Abstract: We’ll describe a new benchmark suite proposed by the Deep Learning community for machine learning workloads. We’ll present a quantitative analysis of an early version (0.5) of benchmark known as MLPerf and explain performance impact of NVIDIA GPU architecture across a range of DL applications. This work includes evaluating MLPerf performance on Turing, Volta, and Pascal to demonstrate the performance impact of NVIDIA GPU architecture across a range of DL applications. We’ll evaluate the impact of system-level technologies — Nvlink vs. PCIe topology — using server- and workstation-class platforms to show how system architecture impacts DL training workloads. We also plan to discuss our work to characterize MLPerf benchmark performance using profiling tools (GPU, CPU, memory & I/O), our hyperparameter tuning study (batch size, learning rate, SGD optimizer) on MLPerf performance, and map real world application use cases to MLPerf suite and how to quantify results for specific DL practitioner use cases. https://gputechconf2019.smarteventscloud.com/connect/sessionDetail.ww?SESSION_ID=263091

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

NSF Budget Approved for $8.3B in 2020, a 2.5% Increase

January 16, 2020

The National Science Foundation (NSF) has been spared a President Trump-proposed budget cut that would have rolled back its funding to 2012 levels. Congress passed legislation last month that sets the budget at $8.3 bill Read more…

By Staff report

NOAA Updates Its Massive, Supercomputer-Generated Climate Dataset

January 15, 2020

As Australia burns, understanding and mitigating the climate crisis is more urgent than ever. Now, by leveraging the computing resources at the National Energy Research Scientific Computing Center (NERSC), the U.S. National Oceanic and Atmospheric Administration (NOAA) has updated its 20th Century Reanalysis Project (20CR) dataset... Read more…

By Oliver Peckham

Atos-AMD System to Quintuple Supercomputing Power at European Centre for Medium-Range Weather Forecasts

January 15, 2020

The United Kingdom-based European Centre for Medium-Range Weather Forecasts (ECMWF), a supercomputer-powered weather forecasting organization backed by most of the countries in Europe, has signed a four-year, $89-million Read more…

By Oliver Peckham

Julia Programming’s Dramatic Rise in HPC and Elsewhere

January 14, 2020

Back in 2012 a paper by four computer scientists including Alan Edelman of MIT introduced Julia, A Fast Dynamic Language for Technical Computing. At the time, the gold standard programming languages for fast performance Read more…

By John Russell

Quantum Computing, ML Drive 2019 Patent Awards

January 14, 2020

The dizzying pace of technology innovation often fueled by the growing availability of computing horsepower is underscored by the race to develop unique designs and application that can be patented. Among the goals of ma Read more…

By George Leopold

AWS Solution Channel

Challenging the barriers to High Performance Computing in the Cloud

Cloud computing helps democratize High Performance Computing by placing powerful computational capabilities in the hands of more researchers, engineers, and organizations who may lack access to sufficient on-premises infrastructure. Read more…

IBM Accelerated Insights

Intelligent HPC – Keeping Hard Work at Bay(es)

Since the dawn of time, humans have looked for ways to make their lives easier. Over the centuries human ingenuity has given us inventions such as the wheel and simple machines – which help greatly with tasks that would otherwise be extremely laborious. Read more…

Andrew Jones Joins Microsoft Azure HPC Team

January 13, 2020

Andrew Jones announced today he is joining Microsoft as part of the Azure HPC engineering & product team in early February. Jones makes the move after nearly 12 years at the UK HPC consultancy Numerical Algorithms Gr Read more…

By Staff report

Atos-AMD System to Quintuple Supercomputing Power at European Centre for Medium-Range Weather Forecasts

January 15, 2020

The United Kingdom-based European Centre for Medium-Range Weather Forecasts (ECMWF), a supercomputer-powered weather forecasting organization backed by most of Read more…

By Oliver Peckham

Julia Programming’s Dramatic Rise in HPC and Elsewhere

January 14, 2020

Back in 2012 a paper by four computer scientists including Alan Edelman of MIT introduced Julia, A Fast Dynamic Language for Technical Computing. At the time, t Read more…

By John Russell

White House AI Regulatory Guidelines: ‘Remove Impediments to Private-sector AI Innovation’

January 9, 2020

When it comes to new technology, it’s been said government initially stays uninvolved – then gets too involved. The White House’s guidelines for federal a Read more…

By Doug Black

IBM Touts Quantum Network Growth, Improving QC Quality, and Battery Research

January 8, 2020

IBM today announced its Q (quantum) Network community had grown to 100-plus – Delta Airlines and Los Alamos National Laboratory are among most recent addition Read more…

By John Russell

HPCwire Awards Highlight Supercomputing Achievements in the Sciences

January 7, 2020

In November at SC19 in Denver, the HPCwire Readers’ and Editors’ Choice awards program celebrated its 16th year of honoring remarkable achievements in high-performance computing. With categories ranging from Best Use of HPC in Energy to Top HPC-Enabled Scientific Achievement, many of the winners contributed to groundbreaking developments in the sciences. This editorial highlights those awards. Read more…

By Oliver Peckham

Blasts from the (Recent) Past and Hopes for the Future

December 23, 2019

What does 2020 look like to you? What did 2019 look like? Lots happened but the main trends were carryovers from 2018 – AI messaging again blanketed everything; the roll-out of new big machines and exascale announcements continued; processor diversity and system disaggregation kicked up a notch; hyperscalers continued flexing their muscles (think AWS and its Graviton2 processor); and the U.S. and China continued their awkward trade war. Read more…

By John Russell

ARPA-E Applies ML to Power Generation Designs

December 19, 2019

The U.S. Energy Department’s research arm is leveraging machine learning technologies to simplify the design process for energy systems ranging from photovolt Read more…

By George Leopold

Focused on ‘Silicon TAM,’ Intel Puts Gary Patton, Former GlobalFoundries CTO, in Charge of Design Enablement

December 12, 2019

Change within Intel’s upper management – and to its company mission – has continued as a published report has disclosed that chip technology heavyweight G Read more…

By Doug Black

Using AI to Solve One of the Most Prevailing Problems in CFD

October 17, 2019

How can artificial intelligence (AI) and high-performance computing (HPC) solve mesh generation, one of the most commonly referenced problems in computational engineering? A new study has set out to answer this question and create an industry-first AI-mesh application... Read more…

By James Sharpe

D-Wave’s Path to 5000 Qubits; Google’s Quantum Supremacy Claim

September 24, 2019

On the heels of IBM’s quantum news last week come two more quantum items. D-Wave Systems today announced the name of its forthcoming 5000-qubit system, Advantage (yes the name choice isn’t serendipity), at its user conference being held this week in Newport, RI. Read more…

By John Russell

SC19: IBM Changes Its HPC-AI Game Plan

November 25, 2019

It’s probably fair to say IBM is known for big bets. Summit supercomputer – a big win. Red Hat acquisition – looking like a big win. OpenPOWER and Power processors – jury’s out? At SC19, long-time IBMer Dave Turek sketched out a different kind of bet for Big Blue – a small ball strategy, if you’ll forgive the baseball analogy... Read more…

By John Russell

Cray, Fujitsu Both Bringing Fujitsu A64FX-based Supercomputers to Market in 2020

November 12, 2019

The number of top-tier HPC systems makers has shrunk due to a steady march of M&A activity, but there is increased diversity and choice of processing compon Read more…

By Tiffany Trader

Crystal Ball Gazing: IBM’s Vision for the Future of Computing

October 14, 2019

Dario Gil, IBM’s relatively new director of research, painted a intriguing portrait of the future of computing along with a rough idea of how IBM thinks we’ Read more…

By John Russell

Julia Programming’s Dramatic Rise in HPC and Elsewhere

January 14, 2020

Back in 2012 a paper by four computer scientists including Alan Edelman of MIT introduced Julia, A Fast Dynamic Language for Technical Computing. At the time, t Read more…

By John Russell

Intel Debuts New GPU – Ponte Vecchio – and Outlines Aspirations for oneAPI

November 17, 2019

Intel today revealed a few more details about its forthcoming Xe line of GPUs – the top SKU is named Ponte Vecchio and will be used in Aurora, the first plann Read more…

By John Russell

Dell Ramps Up HPC Testing of AMD Rome Processors

October 21, 2019

Dell Technologies is wading deeper into the AMD-based systems market with a growing evaluation program for the latest Epyc (Rome) microprocessors from AMD. In a Read more…

By John Russell

Leading Solution Providers

SC 2019 Virtual Booth Video Tour

AMD
AMD
ASROCK RACK
ASROCK RACK
AWS
AWS
CEJN
CJEN
CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
IBM
IBM
MELLANOX
MELLANOX
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
SIX NINES IT
SIX NINES IT
VERNE GLOBAL
VERNE GLOBAL
WEKAIO
WEKAIO

IBM Unveils Latest Achievements in AI Hardware

December 13, 2019

“The increased capabilities of contemporary AI models provide unprecedented recognition accuracy, but often at the expense of larger computational and energet Read more…

By Oliver Peckham

SC19: Welcome to Denver

November 17, 2019

A significant swath of the HPC community has come to Denver for SC19, which began today (Sunday) with a rich technical program. As is customary, the ribbon cutt Read more…

By Tiffany Trader

With the Help of HPC, Astronomers Prepare to Deflect a Real Asteroid

September 26, 2019

For years, NASA has been running simulations of asteroid impacts to understand the risks (and likelihoods) of asteroids colliding with Earth. Now, NASA and the European Space Agency (ESA) are preparing for the next, crucial step in planetary defense against asteroid impacts: physically deflecting a real asteroid. Read more…

By Oliver Peckham

Jensen Huang’s SC19 – Fast Cars, a Strong Arm, and Aiming for the Cloud(s)

November 20, 2019

We’ve come to expect Nvidia CEO Jensen Huang’s annual SC keynote to contain stunning graphics and lively bravado (with plenty of examples) in support of GPU Read more…

By John Russell

Top500: US Maintains Performance Lead; Arm Tops Green500

November 18, 2019

The 54th Top500, revealed today at SC19, is a familiar list: the U.S. Summit (ORNL) and Sierra (LLNL) machines, offering 148.6 and 94.6 petaflops respectively, Read more…

By Tiffany Trader

51,000 Cloud GPUs Converge to Power Neutrino Discovery at the South Pole

November 22, 2019

At the dead center of the South Pole, thousands of sensors spanning a cubic kilometer are buried thousands of meters beneath the ice. The sensors are part of Ic Read more…

By Oliver Peckham

Azure Cloud First with AMD Epyc Rome Processors

November 6, 2019

At Ignite 2019 this week, Microsoft's Azure cloud team and AMD announced an expansion of their partnership that began in 2017 when Azure debuted Epyc-backed instances for storage workloads. The fourth-generation Azure D-series and E-series virtual machines previewed at the Rome launch in August are now generally available. Read more…

By Tiffany Trader

Summit Has Real-Time Analytics: Here’s How It Happened and What’s Next

October 3, 2019

Summit – the world’s fastest publicly-ranked supercomputer – now has real-time streaming analytics. At the 2019 HPC User Forum at Argonne National Laborat Read more…

By Oliver Peckham

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This