BSC Researchers Shrink Floating Point Formats to Accelerate Deep Neural Network Training

By Ken Strandberg

April 15, 2019

Sometimes calculating solutions as precisely as a computer can wastes more CPU resources than is necessary. A case in point is with deep learning. In early stages of training a Deep Neural Network (DNN), a lot of guesswork goes on. The algorithm assigns random values to the weights and computes the error. But the error is enormous in the beginning, and the values of the weights are a long way from the ones selected at the end. Representing weights as a 32-bit floating-point number is costly in terms of processing, yet most of the bits of the mantissa are not needed in early training. As training progresses and it hones the value of the weights, then greater precision becomes important in order to optimize the solution.

Using reduced precision floating point number formats offers benefits in memory footprint and bandwidth and in processing time, which can translate to power savings. These savings can possibly be significant if the benefits can be scaled out to accommodate training of massive DNNs. But will less precision affect overall accuracy of the training?

A lot of research in reduced precision for AI training and inferencing has gone on over the last year. Across Europe and the U.S., industry, academia, and research institutions are looking at this aspect of AI, including U.S. National Labs, Google, and Microsoft. Thus far, the work has resulted in papers, proposals, and some code. Google’s experiments with DNNs have shown that reducing the mantissa in 32-bit floating point numbers for certain calculations of DNNs is okay, “as long as you can represent tiny values closer to zero as part of the summation of small differences during training” (https://en.wikichip.org/wiki/brain_floating-point_format).

Google integrated the bfloat16 format, which provides the same size exponent as the IEEE standard 32-bit FP (float32) but with a smaller mantissa, into some of its products. Bfloat16 is being implemented in a range of future Intel processors for AI deep learning applications.

Intel has integrated a reduced representation format into the Vector Neural Network Instruction (VNNI), a part of Intel Deep Learning Boost (DL Boost), added to the Intel Advanced Vector Extensions 512 instruction set in 2nd generation Xeon Scalable processors.

But the jury is still out on which numbering format or code is best to use at different stages of training and for inferencing. What are the benefits to be gained, in terms of processing performance and power, for the different formats used? And what conditions tell a developer the best format or code to use and when? These are all areas of great interest to Marc Casas, Senior Researcher, at Barcelona Supercomputing Center (BSC).

“We believe dynamic numerical precision approaches offer the best benefit to training and inferencing,” stated Casas. “We are evaluating the applications of many formats and codes, including Intel DL Boost (such as VNNI and others), 32-bit and 64-bit floating point, Flexpoint, and integer formats, at various phases of training neural networks and inferencing.” Flexpoint is a format proposed by Intel for tensors and will be integrated in its Nervana Neural Network processors.

Casas and his team, including John Haiber Osorio Rios and Marc Ortiz of BSC, expect to identify at what phase of training it is best to apply different numerical presentations and how they benefit the network evolution without loss of accuracy. They will also study their impact on processor performance and power consumption on Intel hardware. But, understanding when to use an appropriate format and the impact on the hardware is only one aspect.

“We propose to not only develop innovative ways to exploit the potential of DL Boost and these numerical representations, but to dynamically adjust the Flexpoint/Bfloat16 formats to determine which DL Boost instructions to apply at different phases of training,” add Casas. “We will develop an algorithm to drive these dynamic adjustments based on different proxies describing the network evolution. These adaptive and dynamic schemes used for learning or inferencing phases of DNNs will make it possible to switch across different precisions on runtime.”

Casas says their baseline models are built on Alexnet and Resnet using the Imagenet data set. The project will use software emulations and eventually be applied and evaluated on Intel hardware designed to implement the numerical formats as the next-generation Intel silicon becomes available.

In 2017, BSC installed MareNostrum4, a large supercomputing cluster from Lenovo built on Intel Xeon Scalable processors and Intel Omni-Path Architecture fabric. Casas and his team will use MareNostrum4 to help them answer these questions.

“Understanding the use of dynamic numerical formats and developing schemes to apply them with will change the way industry is training networks,” concluded Casas. “Our work will shed light on allowing a more flexible training mechanism. We will look for ways to apply it to DNN Frameworks, like Intel’s version of Caffe and TensorFlow, so everyone can use it.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

At Long Last, Supercomputing Helps to Map the Poles

August 22, 2019

“For years,” Paul Morin wrote, “those of us that made maps of the Poles apologized. We apologized for the blank spaces on maps, we apologized for mountains being in the wrong place and out-of-date information.” Read more…

By Oliver Peckham

Xilinx Says Its New FPGA is World’s Largest

August 21, 2019

In this age of exploding “technology disaggregation” – in which the Big Bang emanating from the Intel x86 CPU has produced significant advances in CPU chips and a raft of alternative, accelerated architectures... Read more…

By Doug Black

Supercomputers Generate Universes to Illuminate Galactic Formation

August 20, 2019

With advanced imaging and satellite technologies, it’s easier than ever to see a galaxy – but understanding how they form (a process that can take billions of years) is a different story. Now, a team of researchers f Read more…

By Oliver Peckham

AWS Solution Channel

Efficiency and Cost-Optimization for HPC Workloads – AWS Batch and Amazon EC2 Spot Instances

High Performance Computing on AWS leverages the power of cloud computing and the extreme scale it offers to achieve optimal HPC price/performance. With AWS you can right size your services to meet exactly the capacity requirements you need without having to overprovision or compromise capacity. Read more…

HPE Extreme Performance Solutions

Bring the combined power of HPC and AI to your business transformation

FPGA (Field Programmable Gate Array) acceleration cards are not new, as they’ve been commercially available since 1984. Typically, the emphasis around FPGAs has centered on the fact that they’re programmable accelerators, and that they can truly offer workload specific hardware acceleration solutions without requiring custom silicon. Read more…

IBM Accelerated Insights

Keys to Attracting the Newest HPC Talent – Post-Millennials

[Connect with HPC users and learn new skills in the IBM Spectrum LSF User Community.]

For engineers and scientists growing up in the 80s, the current state of HPC makes perfect sense. Read more…

Singularity Moves Up the Container Value Chain

August 20, 2019

The enterprise version of the Singularity HPC container platform released this week by Sylabs is designed to allow users to create, secure and share the high-end containers in self-hosted production deployments. The e Read more…

By George Leopold

At Long Last, Supercomputing Helps to Map the Poles

August 22, 2019

“For years,” Paul Morin wrote, “those of us that made maps of the Poles apologized. We apologized for the blank spaces on maps, we apologized for mountains being in the wrong place and out-of-date information.” Read more…

By Oliver Peckham

IBM Deepens Plunge into Open Source; OpenPOWER to Join Linux Foundation

August 20, 2019

IBM today announced it was contributing the instruction set (ISA) for its Power microprocessor and the designs for the Open Coherent Accelerator Processor Inter Read more…

By John Russell

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a Read more…

By Rob Johnson

AI is the Next Exascale – Rick Stevens on What that Means and Why It’s Important

August 13, 2019

Twelve years ago the Department of Energy (DOE) was just beginning to explore what an exascale computing program might look like and what it might accomplish. Today, DOE is repeating that process for AI, once again starting with science community town halls to gather input and stimulate conversation. The town hall program... Read more…

By Tiffany Trader and John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Lenovo Drives Single-Socket Servers with AMD Epyc Rome CPUs

August 7, 2019

No summer doldrums here. As part of the AMD Epyc Rome launch event in San Francisco today, Lenovo announced two new single-socket servers, the ThinkSystem SR635 Read more…

By Doug Black

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

Cray, AMD to Extend DOE’s Exascale Frontier

May 7, 2019

Cray and AMD are coming back to Oak Ridge National Laboratory to partner on the world’s largest and most expensive supercomputer. The Department of Energy’s Read more…

By Tiffany Trader

Graphene Surprises Again, This Time for Quantum Computing

May 8, 2019

Graphene is fascinating stuff with promise for use in a seeming endless number of applications. This month researchers from the University of Vienna and Institu Read more…

By John Russell

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

A Behind-the-Scenes Look at the Hardware That Powered the Black Hole Image

June 24, 2019

Two months ago, the first-ever image of a black hole took the internet by storm. A team of scientists took years to produce and verify the striking image – an Read more…

By Oliver Peckham

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

Chinese Company Sugon Placed on US ‘Entity List’ After Strong Showing at International Supercomputing Conference

June 26, 2019

After more than a decade of advancing its supercomputing prowess, operating the world’s most powerful supercomputer from June 2013 to June 2018, China is keep Read more…

By Tiffany Trader

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

Qualcomm Invests in RISC-V Startup SiFive

June 7, 2019

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups. Last fall, Esperanto Technologies announced a $58 million funding round. Read more…

By George Leopold

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This