TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

By John Russell

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law.

Shrinking feature size has of course been the primary hallmark of achieving Moore’s law and a recent report in the IEEE Spectrum, written by Samuel Moore, does a nice job of capturing TMSC and Samsung’s early 5nm efforts and posing questions about what’s next. TMSC’s 5nm process, now in so-called “risk production,” reportedly boosts speed 15 percent and achieves 30 percent improvement in power efficiency. Samsung, writes Moore, promises 10 percent speed boost or 20 percent power efficiency.

“Compared, though, with the sometimes 50 percent improvements of a decade ago, it’s clear that Moore’s Law is not what it used to be. But judging by the investments big foundries are making, customers still think it’s worthwhile,” writes Moore, a senior editor for IEEE Spectrum.

Here’s an excerpt from the IEEE article:

“The 5-nm node is the first to be built from the start using extreme ultraviolet lithography (EUV). With a wavelength of just 13.5 nm, EUV light can produce extremely fine patterns on silicon. Some of these patterns could be made with the previous generation of lithographic tools, but those tools would have to lay down three or four different patterns in succession to produce the same result that EUV manages in a single step.

“Foundries began 7-nm manufacturing without EUV, but later used it to collapse the number of lithographic steps and improve yield. At 5 nm, the foundries are thought to be using 10 to 12 EUV steps, which would translate to 30 or more steps in the older technology, if it were even possible to use the older tech.

“Because the photomasks that contain the patterns are so expensive and each lithography machine itself is a US $100 million–plus investment, “EUV costs more per layer,” says G. Dan Hutcheson, at VLSI Research. But it’s a net revenue gap on a per-wafer basis, and EUV will form the core of all future processes.”

So far, TMSC and Samsung are the only foundries offering 5nm. GlobalFoundaries stopped at 14nm and Intel has been late with its next-gen process. Make no mistake, competing at the high-end is expensive. Moore notes in his article that “TSMC’s capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.”

There’s been no shortage of industry conversation around what comes next, in terms of semiconductor manufacturing and in terms of computer architectures to take advantage of the technologies that are available. The Department of Defense’s program, via DARPA – Electronics Resurgence Initiative (ERI) – is a $1.5 billion chip initiative that, according to ERI head William Chappell, seeks to transform the Moore’s law paradigm of the last half-century into “Moore’s Inflection.” Much of ERI’s focus has been on packaging and approaches to design and manufacture of “chiplets” for domain specific tasks.

ERI, like many, is also exploring photonics and its PIPES effort (Photonics in the Package for Extreme Scalability) which addresses the constraints imposed by data movement on current microelectronics, especially power and latency. Using optical rather than electrical components for data transfer is seen as a promising approach for reducing power consumption while increasing data capacity and reducing latency.

Lacking step-function improvements in semiconductor manufacturing it seems likely that many advances will necessarily come from computer architecture and programming. Pioneers John Hennessy and David Patterson, recent winners of ACM’s prestigious Turing Award, offered their optimistic view in a short article, “A New Golden Age for Computer Architecture: Domain-Specific Hardware/Software Co-Design, Enhanced Security, Open Instruction Sets, and Agile Chip Development,” delivered at last June’s International Symposium on Computer Architecture

“We’re on the cusp of another Golden Age that will significantly improve cost, performance, energy, and security. These architecture challenges are even harder given that we’ve lost the exponentially increasing resources provided by Dennard scaling and Moore’s law. We’ve identified areas that are critical to this new age,” wrote the pair citing: co-design; security; free an open architectures; and agile chip development.

With ISC looming (June 16-20) and announcement of the next Top500 list pending, it’s probably a good time to again take stock of Moore’s law and what’s next.

Link to Samuel Moore’s IEEE Spectrum article (Another Step Toward the End of Moore’s Law): https://spectrum.ieee.org/semiconductors/devices/another-step-toward-the-end-of-moores-law

Link to HPCwire article on DoD program (US Chip Initiative Aims For ‘Moore’s (Law) Inflection’): https://www.hpcwire.com/2018/11/08/us-chip-initiative-aims-for-moores-law-inflection/

Link to HPCwire reprint of Hennessy’s and Patterson’s viewpoint (Hennessy & Patterson: A New Golden Age for Computer Architecture): https://www.hpcwire.com/2018/04/17/hennessy-patterson-a-new-golden-age-for-computer-architecture/

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