IEEE Releases Expansive 2018 Roadmap for Devices and Systems

By John Russell

July 24, 2019

IEEE yesterday released the 2018 update to its International Roadmap for Devices and System (IRDS). It’s part history text, part crystal ball, and as IEEE emphasizes, a key reference for the entire electronics value chain. You may remember this report got its start in ~1998 as the International Technology Roadmap for Semiconductors (ITRS) when the focus was squarely on semiconductor technology. It morphed into the IRDS report in 2017 as the decline in Moore’s Law highlighted the rise of many other factors driving computer performance. IEEE and its collaborators responded by expanding the breadth of the report.

As noted in the announcement: “The updated IRDS includes new information on cryogenic electronics and quantum information processing, added benchmarks for applications, and supplemental information and metrics from the More Moore team. In addition, there’s a newly released summary from Beyond CMOS, and updates for emerging devices, outside systems connectivity technology, factory integration (including smart manufacturing and security topics), metrology, and yield enhancement. Market drivers for medical devices and a new automotive market drivers report are also included.”

Let’s say IRDS is more than light summer reading.

On balance, historical information seems most plentiful and many of the projected trends are familiar; nevertheless there’s plenty to dig into. (Check out HPCwire’s coverage of the final ITRS report, Transistors Won’t Shrink Beyond 2021, Says Final ITRS Report) Below is IEEE’s description of the new report:

“The IRDS is a set of predictions that serves as the successor to the ITRS. The intent is to provide a clear outline to simplify academic, manufacturing, supply, and research coordination regarding the development of electronic devices and systems.

“The goals of the roadmap are as follows:

  1. To identify key trends related to devices, systems, and all related technologies by generating a roadmap with a 15-year horizon
  2. To determine generic devices’ and systems’ needs, challenges, potential solutions, and opportunities for innovation
  3. To encourage related activities worldwide through collaborative events, such as related IEEE conferences and roadmap workshops

“The shift and evolution of the roadmap from the ITRS to the IRDS has translated to an expanded focus on systems. Emphasis has been placed on architectures and applications that deviate from the traditional paradigm of device->circuit->logic gate->functional block->system.”

Those are big objectives. Sorting through the report’s high points is beyond the scope of this article. A fair amount of discussion is given to IoT and cloud computing. HPC proper receives a bit less attention. Best to carve out some beach time for reading. It is interesting to note that the 15-year horizon forecast on some of its predictions seems tenuous or directional at best – it’s hard to know much about what 2033 will look like. One example is shown below with explanatory notes at the bottom of the article.

Among IRDS’s extensive contents, it posits a number of Grand Challenges. The lengthy executive summary (~38 pages) provides an overview. Here are a few elements from a Grand Challenge labelled More Moore:

LOGIC DEVICE SCALING
Beyond 2022 a transition from FinFET to gate-all-around (GAA) will start and potentially a transition to vertical nanowires devices will be needed when there will be no room left for the gate length scale down due to the limits of fin width scaling (saturating the Lgate scaling to sustain the electrostatics control) and contact width.

FinFET and lateral GAA devices enable a higher drive at unit footprint if fin pitch can be aggressively scaled while increasing the fin height. This increased drive at unit footprint by scaling the fin pitch comes at a trade-off between fringing capacitance between gate and contact and series resistance. This trend in reducing the number of fins while balancing the drive with increased fin height is defined as fin depopulation strategy, which also simultaneously reduces the standard cell height, therefore the overall chip area.

The most difficult challenge for interconnects is the introduction of new materials that meet the wire conductivity requirements and reduce dielectric permittivity. As for the conductivity, the impact of size effects on interconnect structures must be mitigated. Future effective κ requirements preclude the use of a trench etch stop for dual damascene structures.

DRAM AND 3D NAND FLASH MEMORY
Since the DRAM storage capacitor gets physically smaller with scaling, the EOT (equivalent oxide thickness) must scale down sharply to maintain adequate storage capacitance. To scale the EOT, dielectric materials having high relative dielectric constant (κ) will be needed. Therefore metal-insulator-metal (MIM) capacitors have been adopted using high-κ (ZrO2/Al2O/ZrO2) as the capacitor of 40−30 nm half-pitch DRAM. This material evolution and improvement will continue until 20 nm high- performance (HP) and ultra-high-κ (perovskite κ > 50 ~ 100) materials are released. Also, the physical thickness of the high-κ insulator should be scaled down to fit the minimum feature size. Due to that, capacitor 3D structure will be changed from cylinder to pillar shape.

It’s probably best to think of IRDS as a living document that has grown by accretion, jettisoning little through the years. The result, perhaps necessarily, is the new material seems perhaps a bit thin. Its strength is still on the “semiconductor side” but expansion to systems and more is the right direction.

“The IRDS continues to lead as the go-to reference for researchers, developers and technologists around the world by providing a comprehensive overview of the computer and electronics industry’s trajectory,” said IEEE Fellow Thomas M. Conte, co-chair, IEEE Rebooting Computing Initiative, vice-chair of IRDS, and professor, Georgia Institute of Technology in the official announcement. “The updated IRDS builds upon 16 years of projecting technology needs for the evolving semiconductor and computer industries.”

“The IRDS represents a global effort needed for future computing systems covering many different applications. These worldwide roadmapping activities will allow our community to identify and overcome emerging challenges in this field and to speed-up technology innovation that can drive the development of future markets,” said Francis Balestra, member, Governing Board of the SiNANO Institute, director of research, The French National Center for Scientific Research (CNRS) and vice president of Grenoble Institute of Technology, also quoted in the release.

IRDS partners with regional roadmaps in Europe and Japan. “There are memorandums of understanding (MoUs) with the NanoElectronics Roadmap for Europe: Identification and Dissemination (NEREID, Horizon 2020), of the SiNANO Institute in Europe, and with the Systems and Devices Roadmap committee of Japan (SDRJ) of the Japan Society of Applied Physics,” according to IEEE.

IEEE reports “The updated IRDS can be downloaded by visiting the IRDS home page and joining the IRDS Technical Community. The IRDS is an IEEE Standards Association (IEEE SA) Industry Connections (IC) Program sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative, a program of IEEE Future Directions.”

Link to IEEE release: https://www.businesswire.com/news/home/20190723005052/en/IEEE-Update-International-Roadmap-Devices-Systems-IRDSTM

Link to IRDS page: https://irds.ieee.org

[1]Notes for Table ES2:

ORTC: Logic Notes[1] Based on 0.71x reduction per “Node Range” (“Node” = ~2x Mx).
[2] Based on 0.71x Mx reduction per “Generic Node”, or .5x cell; 2x density; beginning 2013/”G1″/40nm.
[3] Defined as distance between metallurgical source/drain junctions

ORTC: DRAM Notes
[1] The definition of DRAM Half pitch has been changed from this edition. Because of 6F2 DRAM cell, BL pitch is no more critical dimension. pitch= (Cell Area/ Call size factor)^0.5.”
Critical dimension for process development, the Minimum half pitch is also introduced. Currently Active area (long rectangle island shape) half pitch is the critical dimension of 6F2 DRAM.
Calculated half pitch is use the following equation “Calculated half pitch= (Cell Area/ Call size factor)^0.5.” Critical dimension for process development, the Minimum half pitch is also introduced.
Currently Active area (long rectangle island shape) half pitch is the critical dimension of 6F2 DRAM.
[11] Cell size factor = a = (DRAM cell size/F2), where F is the DRAM 1⁄2 pitch. The current values of a are 6 from 2009. And a=4 will be predicted in 2021.

ORTC: NAND Flash Notes
[1] 2D NAND strings consist of closely packed polysilicon control gates (the Word Lines) that separate the source and drain of devices with no internal contact within the cell.
Up to now this uncontacted word line pitch is still the tightest in all technologies.
[6] The number of 3D layers is not a unique function, depending on the cell 1/2 pitch and 3D NAND technology architecture chosen. Lower number of 3D layers generally has lower bit cost,
but other factors such as decoding method, speed performance, easier or harder to get yield, also need to be considered.
The number of 3D layers spans a range since the same density product may be achieved by using smaller 1/2 pitch and fewer layers, or larger 1/2 pitch and more layers.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion XL — were added to the benchmark suite as MLPerf continues Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing power it brings to artificial intelligence.  Nvidia's DGX Read more…

Call for Participation in Workshop on Potential NSF CISE Quantum Initiative

March 26, 2024

Editor’s Note: Next month there will be a workshop to discuss what a quantum initiative led by NSF’s Computer, Information Science and Engineering (CISE) directorate could entail. The details are posted below in a Ca Read more…

Waseda U. Researchers Reports New Quantum Algorithm for Speeding Optimization

March 25, 2024

Optimization problems cover a wide range of applications and are often cited as good candidates for quantum computing. However, the execution time for constrained combinatorial optimization applications on quantum device Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at the network layer threatens to make bigger and brawnier pro Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HBM3E memory as well as the the ability to train 1 trillion pa Read more…

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing po Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HB Read more…

Nvidia Looks to Accelerate GenAI Adoption with NIM

March 19, 2024

Today at the GPU Technology Conference, Nvidia launched a new offering aimed at helping customers quickly deploy their generative AI applications in a secure, s Read more…

The Generative AI Future Is Now, Nvidia’s Huang Says

March 19, 2024

We are in the early days of a transformative shift in how business gets done thanks to the advent of generative AI, according to Nvidia CEO and cofounder Jensen Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

Nvidia Showcases Quantum Cloud, Expanding Quantum Portfolio at GTC24

March 18, 2024

Nvidia’s barrage of quantum news at GTC24 this week includes new products, signature collaborations, and a new Nvidia Quantum Cloud for quantum developers. Wh Read more…

Alibaba Shuts Down its Quantum Computing Effort

November 30, 2023

In case you missed it, China’s e-commerce giant Alibaba has shut down its quantum computing research effort. It’s not entirely clear what drove the change. Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

Shutterstock 1285747942

AMD’s Horsepower-packed MI300X GPU Beats Nvidia’s Upcoming H200

December 7, 2023

AMD and Nvidia are locked in an AI performance battle – much like the gaming GPU performance clash the companies have waged for decades. AMD has claimed it Read more…

DoD Takes a Long View of Quantum Computing

December 19, 2023

Given the large sums tied to expensive weapon systems – think $100-million-plus per F-35 fighter – it’s easy to forget the U.S. Department of Defense is a Read more…

Synopsys Eats Ansys: Does HPC Get Indigestion?

February 8, 2024

Recently, it was announced that Synopsys is buying HPC tool developer Ansys. Started in Pittsburgh, Pa., in 1970 as Swanson Analysis Systems, Inc. (SASI) by John Swanson (and eventually renamed), Ansys serves the CAE (Computer Aided Engineering)/multiphysics engineering simulation market. Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Intel’s Server and PC Chip Development Will Blur After 2025

January 15, 2024

Intel's dealing with much more than chip rivals breathing down its neck; it is simultaneously integrating a bevy of new technologies such as chiplets, artificia Read more…

Baidu Exits Quantum, Closely Following Alibaba’s Earlier Move

January 5, 2024

Reuters reported this week that Baidu, China’s giant e-commerce and services provider, is exiting the quantum computing development arena. Reuters reported � Read more…

Leading Solution Providers

Contributors

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…

Shutterstock 1179408610

Google Addresses the Mysteries of Its Hypercomputer 

December 28, 2023

When Google launched its Hypercomputer earlier this month (December 2023), the first reaction was, "Say what?" It turns out that the Hypercomputer is Google's t Read more…

AMD MI3000A

How AMD May Get Across the CUDA Moat

October 5, 2023

When discussing GenAI, the term "GPU" almost always enters the conversation and the topic often moves toward performance and access. Interestingly, the word "GPU" is assumed to mean "Nvidia" products. (As an aside, the popular Nvidia hardware used in GenAI are not technically... Read more…

Shutterstock 1606064203

Meta’s Zuckerberg Puts Its AI Future in the Hands of 600,000 GPUs

January 25, 2024

In under two minutes, Meta's CEO, Mark Zuckerberg, laid out the company's AI plans, which included a plan to build an artificial intelligence system with the eq Read more…

Google Introduces ‘Hypercomputer’ to Its AI Infrastructure

December 11, 2023

Google ran out of monikers to describe its new AI system released on December 7. Supercomputer perhaps wasn't an apt description, so it settled on Hypercomputer Read more…

China Is All In on a RISC-V Future

January 8, 2024

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled "E Read more…

Intel Won’t Have a Xeon Max Chip with New Emerald Rapids CPU

December 14, 2023

As expected, Intel officially announced its 5th generation Xeon server chips codenamed Emerald Rapids at an event in New York City, where the focus was really o Read more…

IBM Quantum Summit: Two New QPUs, Upgraded Qiskit, 10-year Roadmap and More

December 4, 2023

IBM kicks off its annual Quantum Summit today and will announce a broad range of advances including its much-anticipated 1121-qubit Condor QPU, a smaller 133-qu Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire