Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

By Tiffany Trader

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip using standard CMOS fabrication. At Hot Chips 31 in Stanford, Calif., this week, Ayar Labs will show results of the work it’s been doing with DARPA and Intel on an FPGA chiplet integration platform targeting radar applications.

Ayar Labs, which has offices in Emeryville and Santa Clara, Calif., has just taped out its 11th generation “AL11” electrical-to-optical I/O chiplet, the basis for its commercial product, called TeraPHY, which the company says will enable optical I/O bandwidth capability in excess of a Terabit/sec at 10X lower power than today’s Gigabit/sec I/O solutions.

TeraPHY will be integrated with other silicon technology partners’ designs into multi-chip module (MCM) computing products. In a stroke of good timing for Ayar Labs–which expects early system deployments and prototypes in “reasonable volume” in 2020–there’s something of an MCM/chiplet revolution afoot. Chipmakers, such as Intel and AMD, are turning to the modular packaging approach to sidestep Moore’s law (or maybe Gordon Moore actually foresaw this).

Ayar Labs has been working closely with Intel’s Programmable Solutions Group as part of the DARPA CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) project. At Hot Chips this week, Ayar Labs will be showing its 10th gen chiplet installed in an Intel FPGA package with an Intel Stratix 10 die; and it will also announce its support for the Advanced Interface Bus (AIB) protocol.

ERI Summit (July 16, 2019)

Intel’s Senior Principal Engineer Sergey Shumarayev previewed the new technology at DARPA’s ERI Summit last month. The Ayar Labs chiplet connects to the Intel Stratix 10 FPGA die via the AIB interface using Intel’s EMIB packaging. The Jariet Technologies’ millimeter wave chiplet gets information in through RF, passes that information to the FPGA for pre-processing and that gets shipped out optically via the Ayar Labs chiplet.

The University of Michigan chiplet functions as an AI accelerator. Ayar Labs is not directly involved in the University of Michigan research project, but Ayar Labs Chief Scientist and Co-Founder Mark Wade noted the AI chiplet illustrates the versatility of this type of integration.

“This chiplet package ecosystem allows someone to put in an AI accelerator chip and interface to the FPGA, and then also on the other side interface to our high performance optical IO chip; there’s a kind of transformative joint solution coming together that can be enabled by this emerging ecosystem,” said Wade, who will be presenting at Hot Chips on Tuesday.

Ayar Labs has been working with Intel to evolve AIB — the wide, parallel PHY-level interface that Intel open sourced to help spur chiplet adoption. Freely available on GitHub, AIB is being driven as an open industry standard for enabling low-latency, power-efficient direct chiplet-to-chiplet communication.

Ayar Labs also continues to work on support for serial interfaces, like SerDes — an approach of course that has a lot of momentum behind it. Wade said Ayar’s roadmap now includes a provision for both wide parallel implementations, such as AIB, as well as serial implementations, but he says they are getting the most traction with the wide parallel approach.

Ayar Labs CEO Charlie Wuischpard, who joined the company in November 2018, after heading HPC at Intel for a number of years, told HPCwire that while the FPGA solution being demoed this week is emerging as an Intel technology, the opportunity extends beyond working with a single vendor.

“The fact that the government is standardizing on an electrical interface makes this really suitable for anybody else to pick up and run with,” he said. “We’ve been getting a ton of interest from across the industry as there’s this greater recognition that optical I/O creates whole new sets of opportunities.

Example of a possible heterogeneous system in package (SiP) that combines sensors, proprietary ASIC, FPGA, CPU, Memory, and I/O using AIB as the chiplet interface. (Source: Intel Corp.)

“One of the really interesting things about our technology is not just the innovative optical chiplet that goes in the package, but once you’re relieved of the constraints that are currently in place in system designs around the power and packaging and cooling to drive the massive signals, and that’s the bandwidth over copper, then you can create brand new system architectures,” said Wuischpard.

The FPGA demonstration targets phased array radar applications, which is an important market target for Ayar Labs along with 5G, but Hugo Saleh, vice president of marketing and business development, who also made the jump from Intel, told HPCwire they anticipate another killer app: high-end HPC and AI. Picture, for example, an Nvidia DGX-2 type-box, but instead of the NVLinks, there would be 16 GPUs or AI chips connected by optical interfaces, and then multiple boxes could be connected using optical instead of switched fabrics.

Potential use cases extend to any server with a PCIe card in it. “We’ve got a prototype design where essentially you could take a GPU or an FPGA or an ASIC and build a system the size of a whole rack or maybe multiple racks all optically connected that far expands beyond the 16 GPUs currently supported [in the DGX2],” said Saleh.

The glueless, point-to-point interconnect approach applies for standard two-socket servers, he added. Ayar Labs foresees using optical to create supernodes where every element of the system can talk to every other element of the system, versus going up through a switch.

“We’ve reviewed this with several of the large hyperscale providers and the day we have this capability, they want to start testing it,” said Wuischpard. “We have to be able to first produce our single instance of optically connected FPGA as a first step, but we very rapidly want to move to these new system designs that use optical I/O in a new way.”

AI applications and graph analytics are clamoring for this kind of memory semantic type architecture, and government agencies are looking to leverage the technology for advanced threat intelligence, for identifying patterns in vast and disparate data sets and for tracking objects—like airplanes and drones-in real-time.

Ayar Labs has in its pipeline a graph analytics design win that is using four Ayar Labs chiplets per socket with each one of those chiplets putting out 1.3 Terabits per second of data. “That’s an aggregate of over 5 Terabits per second out of package and the only way they can do this is with optical,” Saleh stated.

In the lab: co-packaged Stratix 10 FPGA and TeraPHY chiplets with fiber connected (courtesy: Ayar Labs)

Ayar Labs works closely with GlobalFoundries, a trusted foundry for the U.S. government. The TeraPHY chips are being manufactured using GloFo’s 45 nanometer RF SOI (Radio Frequency Silicon on Insulator) process, currently at its East Fishkill, NY, facility.

Each optoelectronic chip spans an area of approximately five by eight millimeters. Wade said the sizing takes into account how the chips line up with the Intel FPGA. The Intel chip is a full reticle FPGA die, about 25 millimeters on one edge, and the entire east-west side of that edge has the AIB interface on it. That allows up to three Ayar dies to abut each of those edges, to connect up to the AIB interface and escape all that bandwidth.

“This chiplet kind of revolution that is happening right now really allows a mix and match type of configurability that was not there before,” said Wade. “So it allows you to essentially customize at the package level a chip solution that can be targeted to specific applications. In some cases, you might use an FPGA that doesn’t need every slot populated with an optical I/O chip. So maybe you have a memory chip, maybe you have an AI accelerator chip, maybe you have one of our chiplets. And the beauty is you can mix and match all these things together in a heterogeneous way that previously really was not possible. So this emergence of the chiplet ecosystem is really a big development enabling our type of solution.”

Ayar Labs was founded in 2015 by a group of researchers from MIT, UC Berkeley, and CU Boulder who were part of a 10-year research collaboration funded by DARPA. The company has gone through several funding rounds with an investor roster that includes Playground Global, Intel Capital, Global Foundries, the Founders Fund, Silicon Valley Bank and others. It has also been the recipient of several recent DARPA grants and is involved in the CHIPS and PIPES projects.

Feature image caption: a cameo shot in the lab of Ayar Labs’ TeraPHY chiplet co-packaged with a Stratix 10 FPGA (courtesy: Ayar Labs)

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Graphcore Introduces Next-Gen Intelligence Processing Unit for AI Workloads

July 15, 2020

British hardware designer Graphcore, which emerged from stealth in 2016 to launch its first-generation Intelligence Processing Unit (IPU), has announced its next-generation IPU platform: the IPU-Machine M2000. With the n Read more…

By Oliver Peckham

heFFTe: Scaling FFT for Exascale

July 15, 2020

Exascale computing aspires to provide breakthrough solutions addressing today’s most critical challenges in scientific discovery, energy assurance, economic competitiveness, and national security. This has been the mai Read more…

By Jack Dongarra and Stanimire Tomov

There’s No Storage Like ATGC: Breakthrough Helps to Store ‘The Wizard of Oz’ in DNA

July 15, 2020

Even as storage density reaches new heights, many researchers have their eyes set on a paradigm shift in high-density information storage: storing data in the four nucleotides (A, T, G and C) that constitute DNA, a metho Read more…

By Oliver Peckham

Get a Grip: Intel Neuromorphic Chip Used to Give Robotics Arm a Sense of Touch

July 15, 2020

Moving neuromorphic technology from the laboratory into practice has proven slow-going. This week, National University of Singapore researchers moved the needle forward demonstrating an event-driven, visual-tactile perce Read more…

By John Russell

What’s New in HPC Research: Volcanoes, Mobile Games, Proteins & More

July 14, 2020

In this bimonthly feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here. Read more…

By Oliver Peckham

AWS Solution Channel

INEOS TEAM UK Accelerates Boat Design for America’s Cup Using HPC on AWS

The America’s Cup Dream

The 36th America’s Cup race will be decided in Auckland, New Zealand in 2021. Like all the teams, INEOS TEAM UK will compete in a boat whose design will have followed guidelines set by race organizers to ensure the crew’s sailing skills are fully tested. Read more…

Intel® HPC + AI Pavilion

Supercomputing the Pandemic: Scientific Community Tackles COVID-19 from Multiple Perspectives

Since their inception, supercomputers have taken on the biggest, most complex, and most data-intensive computing challenges—from confirming Einstein’s theories about gravitational waves to predicting the impacts of climate change. Read more…

Joliot-Curie Supercomputer Used to Build First Full, High-Fidelity Aircraft Engine Simulation

July 14, 2020

When industrial designers plan the design of a new element of a vehicle’s propulsion or exterior, they typically use fluid dynamics to optimize airflow and increase the vehicle’s speed and efficiency. These fluid dyn Read more…

By Oliver Peckham

Graphcore Introduces Next-Gen Intelligence Processing Unit for AI Workloads

July 15, 2020

British hardware designer Graphcore, which emerged from stealth in 2016 to launch its first-generation Intelligence Processing Unit (IPU), has announced its nex Read more…

By Oliver Peckham

heFFTe: Scaling FFT for Exascale

July 15, 2020

Exascale computing aspires to provide breakthrough solutions addressing today’s most critical challenges in scientific discovery, energy assurance, economic c Read more…

By Jack Dongarra and Stanimire Tomov

Get a Grip: Intel Neuromorphic Chip Used to Give Robotics Arm a Sense of Touch

July 15, 2020

Moving neuromorphic technology from the laboratory into practice has proven slow-going. This week, National University of Singapore researchers moved the needle Read more…

By John Russell

Max Planck Society Begins Installation of Liquid-Cooled Supercomputer from Lenovo

July 9, 2020

Lenovo announced today that it is supplying a new high performance computer to the Max Planck Society, one of Germany's premier research organizations. Comprise Read more…

By Tiffany Trader

President’s Council Targets AI, Quantum, STEM; Recommends Spending Growth

July 9, 2020

Last week the President Council of Advisors on Science and Technology (PCAST) met (webinar) to review policy recommendations around three sub-committee reports: Read more…

By John Russell

Google Cloud Debuts 16-GPU Ampere A100 Instances

July 7, 2020

On the heels of the Nvidia’s Ampere A100 GPU launch in May, Google Cloud is announcing alpha availability of the A100 “Accelerator Optimized” VM A2 instance family on Google Compute Engine. The instances are powered by the HGX A100 16-GPU platform, which combines two HGX A100 8-GPU baseboards using... Read more…

By Tiffany Trader

Q&A: HLRS’s Bastian Koller Tackles HPC and Industry in Germany and Europe

July 6, 2020

In this exclusive interview for HPCwire – sadly not face to face – Steve Conway, senior advisor for Hyperion Research, talks with Dr.-Ing Bastian Koller about the state of HPC and its collaboration with Industry in Europe. Koller is a familiar figure in HPC. He is the managing director at High Performance Computing Center Stuttgart (HLRS) and also serves... Read more…

By Steve Conway, Hyperion

OpenPOWER Reboot – New Director, New Silicon Partners, Leveraging Linux Foundation Connections

July 2, 2020

Earlier this week the OpenPOWER Foundation announced the contribution of IBM’s A21 Power processor core design to the open source community. Roughly this time Read more…

By John Russell

Supercomputer Modeling Tests How COVID-19 Spreads in Grocery Stores

April 8, 2020

In the COVID-19 era, many people are treating simple activities like getting gas or groceries with caution as they try to heed social distancing mandates and protect their own health. Still, significant uncertainty surrounds the relative risk of different activities, and conflicting information is prevalent. A team of Finnish researchers set out to address some of these uncertainties by... Read more…

By Oliver Peckham

[email protected] Turns Its Massive Crowdsourced Computer Network Against COVID-19

March 16, 2020

For gamers, fighting against a global crisis is usually pure fantasy – but now, it’s looking more like a reality. As supercomputers around the world spin up Read more…

By Oliver Peckham

[email protected] Rallies a Legion of Computers Against the Coronavirus

March 24, 2020

Last week, we highlighted [email protected], a massive, crowdsourced computer network that has turned its resources against the coronavirus pandemic sweeping the globe – but [email protected] isn’t the only game in town. The internet is buzzing with crowdsourced computing... Read more…

By Oliver Peckham

Supercomputer Simulations Reveal the Fate of the Neanderthals

May 25, 2020

For hundreds of thousands of years, neanderthals roamed the planet, eventually (almost 50,000 years ago) giving way to homo sapiens, which quickly became the do Read more…

By Oliver Peckham

DoE Expands on Role of COVID-19 Supercomputing Consortium

March 25, 2020

After announcing the launch of the COVID-19 High Performance Computing Consortium on Sunday, the Department of Energy yesterday provided more details on its sco Read more…

By John Russell

Neocortex Will Be First-of-Its-Kind 800,000-Core AI Supercomputer

June 9, 2020

Pittsburgh Supercomputing Center (PSC - a joint research organization of Carnegie Mellon University and the University of Pittsburgh) has won a $5 million award Read more…

By Tiffany Trader

Honeywell’s Big Bet on Trapped Ion Quantum Computing

April 7, 2020

Honeywell doesn’t spring to mind when thinking of quantum computing pioneers, but a decade ago the high-tech conglomerate better known for its control systems waded deliberately into the then calmer quantum computing (QC) waters. Fast forward to March when Honeywell announced plans to introduce an ion trap-based quantum computer whose ‘performance’ would... Read more…

By John Russell

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

By Doug Black

Leading Solution Providers


Nvidia’s Ampere A100 GPU: Up to 2.5X the HPC, 20X the AI

May 14, 2020

Nvidia's first Ampere-based graphics card, the A100 GPU, packs a whopping 54 billion transistors on 826mm2 of silicon, making it the world's largest seven-nanom Read more…

By Tiffany Trader

‘Billion Molecules Against COVID-19’ Challenge to Launch with Massive Supercomputing Support

April 22, 2020

Around the world, supercomputing centers have spun up and opened their doors for COVID-19 research in what may be the most unified supercomputing effort in hist Read more…

By Oliver Peckham

Australian Researchers Break All-Time Internet Speed Record

May 26, 2020

If you’ve been stuck at home for the last few months, you’ve probably become more attuned to the quality (or lack thereof) of your internet connection. Even Read more…

By Oliver Peckham

15 Slides on Programming Aurora and Exascale Systems

May 7, 2020

Sometime in 2021, Aurora, the first planned U.S. exascale system, is scheduled to be fired up at Argonne National Laboratory. Cray (now HPE) and Intel are the k Read more…

By John Russell

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

TACC Supercomputers Run Simulations Illuminating COVID-19, DNA Replication

March 19, 2020

As supercomputers around the world spin up to combat the coronavirus, the Texas Advanced Computing Center (TACC) is announcing results that may help to illumina Read more…

By Staff report

$100B Plan Submitted for Massive Remake and Expansion of NSF

May 27, 2020

Legislation to reshape, expand - and rename - the National Science Foundation has been submitted in both the U.S. House and Senate. The proposal, which seems to Read more…

By John Russell

John Martinis Reportedly Leaves Google Quantum Effort

April 21, 2020

John Martinis, who led Google’s quantum computing effort since establishing its quantum hardware group in 2014, has left Google after being moved into an advi Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This