Cerebras Debuts AI Supercomputer-on-a-Wafer

By Tiffany Trader

August 27, 2019

Could wafer scale silicon from Cerebras Systems be the first “supercomputer on a chip” worthy of the designation? Last week at Hot Chips at Stanford University, the Silicon Valley startup debuted the largest chip ever built, a 46,225 square millimeter silicon wafer packing 1.2 trillion transistors. Cerebras says the chip’s 400,000 AI-optimized cores can train models 100-1,000 times faster than the current leading AI chip, Nvidia’s V100 GPU.

The Wafer Scale Engine is primarily an AI training machine, aimed to harvest sparsity, so it’s not a supercomputing machine, per se, but like other accelerators, it can work in tandem with and accelerate traditional modeling and simulation workloads. All three of the United States planned exascale-class supercomputers will support AI and data analytics capabilities.

To manufacture its Wafer Scale Engine, which is 57x larger than the current biggest chip (Nvidia’s GV100 GPU), Cerebras, working with TSMC’s 16-nm node, starts with a 300 mm wafer and removes the largest possible square, creating a single silicon chip with 400,000 sparse linear algebra cores, i.e., SLA cores, designed for sparse workloads like deep learning. The integration of these cores into a unified array on a single piece of silicon enables models to be trained in minutes, says Cerebras.

“We can map the entire neural network onto our compute array, we don’t put one layer, save it, another layer, save it. That allows us to achieve model parallel performance and scale linearly,” said Cerebras Founder and CEO Andrew Feldman in an interview with HPCwire. Feldman was the key figure behind Seamicro, which created the Atom-based microserver over a decade ago.

Cerebras’ wafer-scale engine has total of 18 gigabytes of on chip SRAM accessible within a single clock cycle, providing an aggregate 9 petabytes per second of memory bandwidth. An on-chip, all-hardware mesh-connected communication network delivers an aggregate bandwidth of 100 petabits per second.

Yield was one of the biggest challenges that Cerebras’ engineers, working closely with TSMC, had to overcome. Feldman counts it as one of the five major hurdles, along with cross-die connectivity, thermal expansion, packaging and cooling.

“Those were historically the five reasons why in the past 60 years, nobody could make one of these,” he said. “Cross-die connectivity and yield were the hardest. Once you’ve you succeeded, in that, you had to grapple with thermal expansion, packaging and cooling.”

Cerebras’ Wafer Scale Engine is comprised of 84 processing tiles, acting as one device

Cerebras invented a technique as part of the lithographic process to lay thousands of communications links across every scribe line. The result, said Feldman, is that rather than behaving like one-hundred chips [84 specifically], the wafer-scale engine behaves like 400,000 cores. “The software has no knowledge of whether it’s on one chip or another chip; it just sees this array,” the CEO said. Cerebras collaborated with TSMC for more than two years to develop the necessary lithographic techniques.

Cerebras can reportedly yield every wafer that TSMC delivers; 100 percent yield. An array of repeated identical tiles is built into the wafer, resulting in 400,000 very small cores, enabling redundancy.

“When it comes to yield, redundancy is your friend,” said Sean Li, chief architect and co-founder, in his Hot Chips talk.

Only 1.5 percent of the overall die is dedicated to spare cores and links, and flaws can be circumvented using these spares.

The next challenge was getting this wafer-size chip onto a motherboard, and dealing with the coefficient of thermal expansion; in other words how do you prevent a silicon chip this size from cracking as the fiberglass printed circuit board expands? Cerebras says it invented a material and a new type of connector to absorb some of that difference even when the two elements were no longer plumb.

Cerebras Wafer Scale Engine (WSE) manufacturing process

Nearly every step of the manufacturing process had to be rethought and customized. “Now that we had the silicon connector, and a printed circuit board, we had another problem nobody else had ever encountered, which is nobody’s been able to package this,” said Feldman. “Nobody had a cold plate for it. Nobody knew how to design a PCB that was appropriate for it. And there were no tools in the manufacturing supply chain that allowed us to achieve the alignment we needed, that had the handling…. We had to invent tools that carried a wafer, we had to invent equipment to qualify and test whole wafers. We had to invent the software that did alignment, all of this so that we could yield a wafer. The final problem was how do you power and how do you cool it.”

The chip is too large for power or cooling to be sent across horizontally, so a third dimension, what Cerebras calls the Z dimension, was used in both cases. With this technique, power isn’t delivered across the PCB, it’s delivered through it. The PCBs have thousands of little holes, through-silicon-vias, and power is delivered through the via so the distance is not very far.

For cooling, rather than running cool water or air across it, cool water is punched down using a copper cold plate with a grid of tiny fins. Each die reticle cooling area contains about 100 fins, so that’s roughly 840 fins ferrying away the heat. The liquid drops down into a heat exchanger that uses air to cool the water. First-gen cold plate technology is not for the faint of heart, but Cerebras reports they’ve had it working “for years” now.

Cerebras has a full system under development and says it has been running customer workloads for months; its first customer shipment is scheduled for early September. Cerebras expects to reveal details of its system at Supercomputing in November with customers in the HPC/supercomputing space. The company reports it is currently clustering its wafer-scale chip nodes, using 100 Gigabit Ethernet.

Hopefully we’ll learn the clock speed of the chip as well as the power consumption for the complete system when it is announced. It’s been estimated that the chip will use 14-15 kilowatts of power, which isn’t unreasonable if it can really do the AI training work of 100-1,000 GPUs. As a point of comparison, the DGX-2 has a max power draw of 10 kilowatts — necessary to drive the 16 V100s, a couple Platinum Xeons, the NVSwitch, eight InfiniBand ports, plus NVMe storage.

Cerebras has been quietly developing its technology since 2015; it has secured $112 million in venture funding and has a staff of nearly 200. CEO Feldman, Chief Architect Sean Li, CTO Gary Lauterback and others in the core leadership team all hail from Seamicro, which was acquired by AMD in 2012 for $355 million.

“We got a little bit lucky in 2007, when Gary and I started Seamicro, but hardware was at a nadir in the valley. Every venture capitalist had their new guy from VMware, who just thought the answer was another virtual machine, and didn’t understand hardware at all. By 2016, we were back on the rise. And people understood that if you want to go fast, you need [better] hardware,” said Feldman.

“And so there was a willingness to engage in new architectures and willingness to engage in new system design, and that’s really important. I don’t think you can achieve the type of performance that we aspire to if you just build a chip; you’re going to put it in somebody else’s server, and you’re going to put your Ferrari in a Volkswagen chassis. And you’re going to get Volkswagen performance. If you want to build a Ferrari, you need to think about how to feed it. And its handling and its steering and every last aspect. And that’s why we’re system builders; that’s what we thought we needed to do to do this.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

With New Owner and New Roadmap, an Independent Omni-Path Is Staging a Comeback

July 23, 2021

Put on a shelf by Intel in 2019, Omni-Path faced a uncertain future, but under new custodian Cornelis Networks, OmniPath is looking to make a comeback as an independent high-performance interconnect solution. A "significant refresh" – called Omni-Path Express – is coming later this year according to the company. Cornelis Networks formed last September as a spinout of Intel's Omni-Path division. Read more…

PEARC21 Panel Reviews Eight New NSF-Funded HPC Systems Debuting in 2021

July 23, 2021

Over the past few years, the NSF has funded a number of HPC systems to further supply the open research community with computational resources to meet that community’s changing and expanding needs. A review of these systems at the PEARC21 conference (July 19-22) highlighted... Read more…

Chameleon’s HPC Testbed Sharpens Its Edge, Presses ‘Replay’

July 22, 2021

“One way of saying what I do for a living is to say that I develop scientific instruments,” said Kate Keahey, a senior fellow at the University of Chicago and a computer scientist at Argonne National Laboratory, as s Read more…

PEARC21 Plenary Session: AI for Innovative Social Work

July 21, 2021

AI analysis of social media poses a double-edged sword for social work and addressing the needs of at-risk youths, said Desmond Upton Patton, senior associate dean, Innovation and Academic Affairs, Columbia University. S Read more…

Summer Reading: “High-Performance Computing Is at an Inflection Point”

July 21, 2021

At last month’s 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), a group of researchers led by Martin Schulz of the Leibniz Supercomputing Center (Munich) presented a “position paper” in which they argue HPC architectural landscape... Read more…

AWS Solution Channel

Accelerate innovation in healthcare and life sciences with AWS HPC

With Amazon Web Services, researchers can access purpose-built HPC tools and services along with scientific and technical expertise to accelerate the pace of discovery. Whether you are sequencing the human genome, using AI/ML for disease detection or running molecular dynamics simulations to develop lifesaving drugs, AWS has the infrastructure you need to run your HPC workloads. Read more…

PEARC21 Panel: Wafer-Scale-Engine Technology Accelerates Machine Learning, HPC

July 21, 2021

Early use of Cerebras’ CS-1 server and wafer-scale engine (WSE) has demonstrated promising acceleration of machine-learning algorithms, according to participants in the Scientific Research Enabled by CS-1 Systems panel Read more…

With New Owner and New Roadmap, an Independent Omni-Path Is Staging a Comeback

July 23, 2021

Put on a shelf by Intel in 2019, Omni-Path faced a uncertain future, but under new custodian Cornelis Networks, OmniPath is looking to make a comeback as an independent high-performance interconnect solution. A "significant refresh" – called Omni-Path Express – is coming later this year according to the company. Cornelis Networks formed last September as a spinout of Intel's Omni-Path division. Read more…

Chameleon’s HPC Testbed Sharpens Its Edge, Presses ‘Replay’

July 22, 2021

“One way of saying what I do for a living is to say that I develop scientific instruments,” said Kate Keahey, a senior fellow at the University of Chicago a Read more…

Summer Reading: “High-Performance Computing Is at an Inflection Point”

July 21, 2021

At last month’s 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), a group of researchers led by Martin Schulz of the Leibniz Supercomputing Center (Munich) presented a “position paper” in which they argue HPC architectural landscape... Read more…

PEARC21 Panel: Wafer-Scale-Engine Technology Accelerates Machine Learning, HPC

July 21, 2021

Early use of Cerebras’ CS-1 server and wafer-scale engine (WSE) has demonstrated promising acceleration of machine-learning algorithms, according to participa Read more…

15 Years Later, the Green500 Continues Its Push for Energy Efficiency as a First-Order Concern in HPC

July 15, 2021

The Green500 list, which ranks the most energy-efficient supercomputers in the world, has virtually always faced an uphill battle. As Wu Feng – custodian of the Green500 list and an associate professor at Virginia Tech – tells it, “noone" cared about energy efficiency in the early 2000s, when the seeds... Read more…

Frontier to Meet 20MW Exascale Power Target Set by DARPA in 2008

July 14, 2021

After more than a decade of planning, the United States’ first exascale computer, Frontier, is set to arrive at Oak Ridge National Laboratory (ORNL) later this year. Crossing this “1,000x” horizon required overcoming four major challenges: power demand, reliability, extreme parallelism and data movement. Read more…

Quantum Roundup: IBM, Rigetti, Phasecraft, Oxford QC, China, and More

July 13, 2021

IBM yesterday announced a proof for a quantum ML algorithm. A week ago, it unveiled a new topology for its quantum processors. Last Friday, the Technical Univer Read more…

ExaWind Prepares for New Architectures, Bigger Simulations

July 10, 2021

The ExaWind project describes itself in terms of terms like wake formation, turbine-turbine interaction and blade-boundary-layer dynamics, but the pitch to the Read more…

AMD Chipmaker TSMC to Use AMD Chips for Chipmaking

May 8, 2021

TSMC has tapped AMD to support its major manufacturing and R&D workloads. AMD will provide its Epyc Rome 7702P CPUs – with 64 cores operating at a base cl Read more…

Intel Launches 10nm ‘Ice Lake’ Datacenter CPU with Up to 40 Cores

April 6, 2021

The wait is over. Today Intel officially launched its 10nm datacenter CPU, the third-generation Intel Xeon Scalable processor, codenamed Ice Lake. With up to 40 Read more…

Berkeley Lab Debuts Perlmutter, World’s Fastest AI Supercomputer

May 27, 2021

A ribbon-cutting ceremony held virtually at Berkeley Lab's National Energy Research Scientific Computing Center (NERSC) today marked the official launch of Perlmutter – aka NERSC-9 – the GPU-accelerated supercomputer built by HPE in partnership with Nvidia and AMD. Read more…

Ahead of ‘Dojo,’ Tesla Reveals Its Massive Precursor Supercomputer

June 22, 2021

In spring 2019, Tesla made cryptic reference to a project called Dojo, a “super-powerful training computer” for video data processing. Then, in summer 2020, Tesla CEO Elon Musk tweeted: “Tesla is developing a [neural network] training computer called Dojo to process truly vast amounts of video data. It’s a beast! … A truly useful exaflop at de facto FP32.” Read more…

Google Launches TPU v4 AI Chips

May 20, 2021

Google CEO Sundar Pichai spoke for only one minute and 42 seconds about the company’s latest TPU v4 Tensor Processing Units during his keynote at the Google I Read more…

CentOS Replacement Rocky Linux Is Now in GA and Under Independent Control

June 21, 2021

The Rocky Enterprise Software Foundation (RESF) is announcing the general availability of Rocky Linux, release 8.4, designed as a drop-in replacement for the soon-to-be discontinued CentOS. The GA release is launching six-and-a-half months after Red Hat deprecated its support for the widely popular, free CentOS server operating system. The Rocky Linux development effort... Read more…

CERN Is Betting Big on Exascale

April 1, 2021

The European Organization for Nuclear Research (CERN) involves 23 countries, 15,000 researchers, billions of dollars a year, and the biggest machine in the worl Read more…

Iran Gains HPC Capabilities with Launch of ‘Simorgh’ Supercomputer

May 18, 2021

Iran is said to be developing domestic supercomputing technology to advance the processing of scientific, economic, political and military data, and to strengthen the nation’s position in the age of AI and big data. On Sunday, Iran unveiled the Simorgh supercomputer, which will deliver.... Read more…

Leading Solution Providers

Contributors

HPE Launches Storage Line Loaded with IBM’s Spectrum Scale File System

April 6, 2021

HPE today launched a new family of storage solutions bundled with IBM’s Spectrum Scale Erasure Code Edition parallel file system (description below) and featu Read more…

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

GTC21: Nvidia Launches cuQuantum; Dips a Toe in Quantum Computing

April 13, 2021

Yesterday Nvidia officially dipped a toe into quantum computing with the launch of cuQuantum SDK, a development platform for simulating quantum circuits on GPU-accelerated systems. As Nvidia CEO Jensen Huang emphasized in his keynote, Nvidia doesn’t plan to build... Read more…

Microsoft to Provide World’s Most Powerful Weather & Climate Supercomputer for UK’s Met Office

April 22, 2021

More than 14 months ago, the UK government announced plans to invest £1.2 billion ($1.56 billion) into weather and climate supercomputing, including procuremen Read more…

Q&A with Jim Keller, CTO of Tenstorrent, and an HPCwire Person to Watch in 2021

April 22, 2021

As part of our HPCwire Person to Watch series, we are happy to present our interview with Jim Keller, president and chief technology officer of Tenstorrent. One of the top chip architects of our time, Keller has had an impactful career. Read more…

Quantum Roundup: IBM, Rigetti, Phasecraft, Oxford QC, China, and More

July 13, 2021

IBM yesterday announced a proof for a quantum ML algorithm. A week ago, it unveiled a new topology for its quantum processors. Last Friday, the Technical Univer Read more…

Senate Debate on Bill to Remake NSF – the Endless Frontier Act – Begins

May 18, 2021

The U.S. Senate today opened floor debate on the Endless Frontier Act which seeks to remake and expand the National Science Foundation by creating a technology Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire