Deep Learning on GPUs: Successes and Promises

By Sparsh Mittal

August 27, 2019

The rise of deep-learning (DL) has been fueled by the improvements in accelerators. Accelerators allow DL models to crunch a large amount of data, which is vital for them to achieve high accuracy. In fact, AlexNet, the famous winner of the ILSVRC 2012 competition, was trained on GPUs. GPU continues to remain the most widely used accelerator for DL applications, due to several of its features, such as high performance, continued improvements in its architecture and software-stack, ease of programming using high-level languages such as CUDA and availability of GPUs in cloud.

“Accelerating DL models” is chasing a moving target

As DL models are becoming more pervasive and accurate, their compute and memory requirements are growing tremendously. For example, training a deep neural network (DNN) takes a large amount of time, e.g., 100-epoch training of ResNet-50 on ImageNet dataset on one M40 GPU requires 14 days. Similarly, during inference, meeting the latency targets while achieving high data-reuse and throughput is a major challenge.

Extracting last bit of performance from GPU

While treating GPU as a black box is a convenient abstraction of DL researchers, even simple architectural optimizations can boost the performance of GPU significantly. For example, since the input-data to DNN remains unchanged, it can be stored in the constant cache. The weights can be loaded in shared memory to avoid incurring the penalty of accessing global memory. Also, partial sums can be stored in the register file to achieve efficient accumulation.

In fact, architecture-oblivious techniques run the risk of losing their theoretical benefits. For example, although weight pruning is expected to increase performance by virtue of reducing the model size of a DNN, on GPUs, pruning actually harms the performance of DNNs. This is because weight pruning makes the DNN sparse, which requires sparse matrix-multiplication (MM). However, optimizations such as memory-coalescing and matrix tiling cannot be performed on sparse MM. To address this inefficiency, researchers suggest doing “node pruning,” and not “weight pruning” on GPU.

Node pruning does not make the network sparse, and although it brings a smaller reduction in model size than weight pruning, it achieves higher throughput by more effectively utilizing the massive resources of GPUs.

Similarly, optimizing data-layouts, batching, and data-reuse is important to get high performance. Also, since convolution can be performed in multiple ways such as FFT, Winograd, lowering (matrix-multiplication) or direct convolution, the choice of the right strategy is essential. The recent survey paper I’ve written with Shraiysh Vaishay reviews many techniques for optimizing DL on GPUs.

Utilizing both CPU memory and GPU memory

DNN training requires a significant amount of memory, which may exceed the memory capacity of a single GPU. For example, training VGG-16 with a batch size of 256 requires 28GB memory, which is larger than the 12GB memory capacity of Titan X.

To alleviate the memory bottleneck issue, the memory resources of CPUs can be used. In the back-propagation algorithm, the feature maps of a layer, which are produced during the forward-propagation phase, are later reused during the backward-propagation phase of the same layer. Since current machine-learning frameworks allocate the memory for accommodating the needs of all the layers, these feature maps stay in GPU memory for a long time without getting used. To alleviate this inefficiency, feature maps not required by the current layer in the forward-propagation phase are offloaded to CPU memory and released from GPU memory. During the backward propagation phase, these feature maps are fetched from CPU memory to GPU memory just before the processing of that layer. Evidently, the GPU memory management techniques and high-bandwidth interconnect such as NVLink can play a significant role in accelerating training of DNN workloads.

HPC is vital for AI

Distributed computing over a cluster of GPUs can reduce the training time of DNNs significantly. For example, researchers from SenseTime Research and Nanyang Technological University, Singapore have trained AlexNet over ImageNet dataset in just 1.5 minutes. They have used a cluster of 64 machines, each with 8 Volta GPUs. They also perform a range of optimizations at all levels of abstraction, such as using NVIDIA’s NCCL communication library and storing parameters and gradients in half-precision (FP16). Also, they overlap the communication of gradient of one layer with backward propagation of subsequent layers, combine multiple allreduce operations into one operation to reduce the memory copy overhead and intelligently transmit only those gradients that exceed a threshold.

Similarly, researchers from Sony corporation have trained ResNet-50 in just 2 minutes using 3,456 Volta GPUs. This “race to train DNNs” is no less exciting than the “race to the moon” seen in the 1960s! On a more serious note, the DNN training performance can be a more meaningful metric for HPC systems than the peak performance metrics such as Exaflop. This has already led to the creation of benchmarks such as DawnBench and MLPerf.

AI accelerator future promises to be exciting

While the general-purpose nature of GPU makes it useful for a broad range of applications, it also precludes thorough optimization of GPU architecture for AI applications. In this regard, custom-made AI accelerators such as Google’s tensor processing unit (TPU) are in a vantage position. It remains to be seen whether the future trajectory of GPU architecture will see revolutionary or evolutionary changes. It will be also interesting to see how well the next-generation GPU strikes a balance between the conflicting goals of special-purpose and general-purpose computing, and how well it competes with the other AI accelerators.

About the Author

Sparsh Mittal received the B.Tech. degree in electronics and communications engineering from IIT, Roorkee, India and the Ph.D. degree in computer engineering from Iowa State University (ISU), USA. He worked as a Post-Doctoral Research Associate at Oak Ridge National Lab (ORNL), USA for 3 years. He is currently working as an assistant professor at IIT Hyderabad, India. He was the graduating topper of his batch in B.Tech and has received fellowship from ISU and performance award from ORNL. Sparsh has published more than 70 papers in top conferences and journals. His research interests include accelerators for machine learning, non-volatile memory, and GPU architectures. His webpage is http://www.iith.ac.in/~sparsh/

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing power it brings to artificial intelligence.  Nvidia's DGX Read more…

Call for Participation in Workshop on Potential NSF CISE Quantum Initiative

March 26, 2024

Editor’s Note: Next month there will be a workshop to discuss what a quantum initiative led by NSF’s Computer, Information Science and Engineering (CISE) directorate could entail. The details are posted below in a Ca Read more…

Waseda U. Researchers Reports New Quantum Algorithm for Speeding Optimization

March 25, 2024

Optimization problems cover a wide range of applications and are often cited as good candidates for quantum computing. However, the execution time for constrained combinatorial optimization applications on quantum device Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at the network layer threatens to make bigger and brawnier pro Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HBM3E memory as well as the the ability to train 1 trillion pa Read more…

Nvidia Appoints Andy Grant as EMEA Director of Supercomputing, Higher Education, and AI

March 22, 2024

Nvidia recently appointed Andy Grant as Director, Supercomputing, Higher Education, and AI for Europe, the Middle East, and Africa (EMEA). With over 25 years of high-performance computing (HPC) experience, Grant brings a Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing po Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HB Read more…

Nvidia Looks to Accelerate GenAI Adoption with NIM

March 19, 2024

Today at the GPU Technology Conference, Nvidia launched a new offering aimed at helping customers quickly deploy their generative AI applications in a secure, s Read more…

The Generative AI Future Is Now, Nvidia’s Huang Says

March 19, 2024

We are in the early days of a transformative shift in how business gets done thanks to the advent of generative AI, according to Nvidia CEO and cofounder Jensen Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

Nvidia Showcases Quantum Cloud, Expanding Quantum Portfolio at GTC24

March 18, 2024

Nvidia’s barrage of quantum news at GTC24 this week includes new products, signature collaborations, and a new Nvidia Quantum Cloud for quantum developers. Wh Read more…

Houston We Have a Solution: Addressing the HPC and Tech Talent Gap

March 15, 2024

Generations of Houstonian teachers, counselors, and parents have either worked in the aerospace industry or know people who do - the prospect of entering the fi Read more…

Alibaba Shuts Down its Quantum Computing Effort

November 30, 2023

In case you missed it, China’s e-commerce giant Alibaba has shut down its quantum computing research effort. It’s not entirely clear what drove the change. Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

Shutterstock 1285747942

AMD’s Horsepower-packed MI300X GPU Beats Nvidia’s Upcoming H200

December 7, 2023

AMD and Nvidia are locked in an AI performance battle – much like the gaming GPU performance clash the companies have waged for decades. AMD has claimed it Read more…

DoD Takes a Long View of Quantum Computing

December 19, 2023

Given the large sums tied to expensive weapon systems – think $100-million-plus per F-35 fighter – it’s easy to forget the U.S. Department of Defense is a Read more…

Synopsys Eats Ansys: Does HPC Get Indigestion?

February 8, 2024

Recently, it was announced that Synopsys is buying HPC tool developer Ansys. Started in Pittsburgh, Pa., in 1970 as Swanson Analysis Systems, Inc. (SASI) by John Swanson (and eventually renamed), Ansys serves the CAE (Computer Aided Engineering)/multiphysics engineering simulation market. Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Intel’s Server and PC Chip Development Will Blur After 2025

January 15, 2024

Intel's dealing with much more than chip rivals breathing down its neck; it is simultaneously integrating a bevy of new technologies such as chiplets, artificia Read more…

Baidu Exits Quantum, Closely Following Alibaba’s Earlier Move

January 5, 2024

Reuters reported this week that Baidu, China’s giant e-commerce and services provider, is exiting the quantum computing development arena. Reuters reported � Read more…

Leading Solution Providers

Contributors

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…

Shutterstock 1179408610

Google Addresses the Mysteries of Its Hypercomputer 

December 28, 2023

When Google launched its Hypercomputer earlier this month (December 2023), the first reaction was, "Say what?" It turns out that the Hypercomputer is Google's t Read more…

AMD MI3000A

How AMD May Get Across the CUDA Moat

October 5, 2023

When discussing GenAI, the term "GPU" almost always enters the conversation and the topic often moves toward performance and access. Interestingly, the word "GPU" is assumed to mean "Nvidia" products. (As an aside, the popular Nvidia hardware used in GenAI are not technically... Read more…

Shutterstock 1606064203

Meta’s Zuckerberg Puts Its AI Future in the Hands of 600,000 GPUs

January 25, 2024

In under two minutes, Meta's CEO, Mark Zuckerberg, laid out the company's AI plans, which included a plan to build an artificial intelligence system with the eq Read more…

Google Introduces ‘Hypercomputer’ to Its AI Infrastructure

December 11, 2023

Google ran out of monikers to describe its new AI system released on December 7. Supercomputer perhaps wasn't an apt description, so it settled on Hypercomputer Read more…

China Is All In on a RISC-V Future

January 8, 2024

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled "E Read more…

Intel Won’t Have a Xeon Max Chip with New Emerald Rapids CPU

December 14, 2023

As expected, Intel officially announced its 5th generation Xeon server chips codenamed Emerald Rapids at an event in New York City, where the focus was really o Read more…

IBM Quantum Summit: Two New QPUs, Upgraded Qiskit, 10-year Roadmap and More

December 4, 2023

IBM kicks off its annual Quantum Summit today and will announce a broad range of advances including its much-anticipated 1121-qubit Condor QPU, a smaller 133-qu Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire