When in Rome: AMD Announces New Epyc CPU for HPC, Server and Cloud Wins

By John Russell

September 18, 2019

Where else but Rome could AMD hold the official Europe launch party for its second generation of Epyc microprocessors, codenamed Rome. Today, AMD did just that announcing key server wins, important cloud provider wins – including IBM Cloud – introduction of a new 64-core, 280-watt CPU aimed at high-end HPC, and indulging in some chest-thumping around performance metrics. And that’s not all. Yesterday, Dell EMC announced five new servers based on second-gen Epyc.

You get the picture. For AMD recently, it’s been (almost) all sunshine and haymaking. There’s also been a noticeable shift in positioning. When AMD plunged back into the datacenter market in 2017, contrition for past error and emphasis on competitive TCO (cum solid technology) were the main talking points. That’s changing as AMD seeks to add technology leadership to the message mix and cash in on its delivery of 7nm promises and product roadmap while Intel stumbles a bit.

In his media pre-briefing yesterday, Scott Aylor tackled technology achievement first. “One of the major themes in San Francisco” at the official launch of the Rome line roughly six weeks ago, “was [our] 80 World Records and counting,” he said. “We’re excited to say that number is going to be eclipsed. We don’t have the final count but know it will be north of 100.”

Last week at Tabor Communication’s conference, HPC &AI on Wall St., Aylor told HPCwire, “We think about pivoting from a TCO oriented play in the market to a leadership performance position that, by the way, has a fantastic TCO.” Rome, AMD hopes, is the platform to start accomplishing that goal.

Here’s a tech snapshot: The second-gen Epyc SoCs are built as nine-die packages with eight 7nm complex core die (CCD) chiplets — with up to eight cores each — surrounding a 14nm I/O die, connected via AMD’s second-gen Infinity fabric. AMD says the next-generation Infinity architecture gives customers access to the most I/O and memory bandwidth in its class, with 128 lanes of PCIe generation 4 (or more in custom builds). The upgraded fabric nearly doubles throughput, pushing 18GT/s socket-to-socket compared with 10.7 GT/s of throughput in the first generation chips.

It’s still good to remember AMD has a smaller waterfront to guard than larger rival Intel and that AMD’s market share remains in single digits although the company has aspirations for double digits in a year or so. In terms of technology, there wasn’t much new revealed at today’s Europe event that hadn’t been disclosed at the US launch. (For a deeper dive into second-gen Epyc’s technology, see HPCwire coverage, AMD Launches Epyc Rome, First 7nm CPU).

For the HPC community, release of the new sku – 7H12 – is perhaps most interesting news. It is nearly the same as the 7742 part but has 280W TDP (+55W); 2.6 GHz base (+350 MHz); 3.3 GHz boost (-100 MHz). The new sku is designed to leverage water cooled systems and is already used by Atos in the BullSequana XH 2000. Aylor noted it’s a “hugely dense platform with the ability to put eight processors essentially in 1U form factor.” The BullSequana XH2000 supports other microprocessors as well, including Intel and Arm (Marvell ThunderX2), and Nvidia GPUs for accelerators.

Atos BullSequana XH2000 supercomputer

Atos has lined up customers for Epyc-based versions of the BullSequana XH2000 – CSC, Finland (7-plus petaflops system), Uninett, Norway (6 petaflops), and GENCi, France (12 petaflops). Moreover, Atos today announced publishing the top results for two-socket nodes on four SPECrate benchmarks and set a new record for the HPL Linpack Benchmark.

Atos issued the following statement: “We’re extremely proud that our BullSequana has achieved these world-record results. Our unique Enhanced Direct Liquid Cooling system provided the most efficient environment for achieving such performance of the AMD EPYC processor,” said Agnès Boudot, SVP, head of HPC & Quantum at Atos. “Our BullSequana equipped with the latest AMD chip, provides our customers with the highest available performance for HPC and AI workloads, with an optimized TCO, to support them in going beyond the limits of traditional simulation.”

Supermicro will also offer systems based on the 7H12 (Ultra & GPU platforms) which are scheduled to be available in Q4 2019. The 7H12 will be broadly available to the market according to Aylor.

On the cloud front, AMD announced IBM Cloud would offer Epyc-based instances. “We have been in in close partnership with IBM Cloud for a long time,” said Aylor. In terms of matching second-gen Epyc to IBM needs, he said, “Think about things like very large container implementations, very high performance bare metal implementations, as well as virtualized environments.”

OVHcloud, a dominant player in Europe, also announced it would use second-gen Epyc. “[They will offer] the 7402P as part of their dedicated hosting environment, leveraging a full flash implementation with direct connect via NVMe to the 7402P which is a single socket solution. And again, looking at driving this in terms of virtualization, so containers really optimized on greatest level of density and thinking about computing economics,” said Aylor. Availability of these instances is expected by EOY 2019.

AMD’s first-gen Epyc has already enjoyed wide success among cloud providers, particularly in pushing 1-socket solutions. The hope is the second-gen devices will do as well. Google and Azure have announced plans to use second-gen Epyc. In his pre-briefing Aylor set high expectation for further adoptions, “You can also see some of the folks that have been on stage with us and can kind of assume where they’re headed. It’s also worth noting that we have a China event in the middle of October where I think there will be substantial news based upon some of the major players in China.”

The Dell EMC news – released yesterday and also discussed at today’s AMD event – had been expected. It included two single-socket and three dual-socket PowerEdge servers based on second-gen Epyc. HPCwire’s sister pub, EnterpriseAI reported yesterday: “With an eye on HPC going mainstream, Ravi Pendekanti (Dell EMC SVP, server infrastructure) said the high-end, two-socket model achieved 3,462 Gigaflops, representing a more than 200-percent performance upgrade based on the Linpack benchmark. Those performance benchmarks grew out of earlier development at Dell EMC’s recently formed HPC and AI Innovation Lab.” (For more see coverage, Dell’s AMD-Powered Server Line Targets High-End Jobs)

The last prominent win previewed by Aylor was Nokia’s decision to use second-gen Epyc processors. AMD reported Nokia will use Epyc to “accelerate its Cloud Packet Core system which helps service providers deliver converged broadband, IoT, and machine-type communication services for 5G.” According to AMD, during testing Nokia was able to get a 2X increase in packet throughput compared to previous systems.

Given the seemingly rapid market traction for second-gen Epyc, there have been reports of concern around meeting demand. AMD seemed to be addressing that by announcing a multi-generation partnership with its fab TSMC (Taiwan Semiconductor Manufacturing Co.) as well as announcing TSMC’s decision to use second-gen Epyc in its own datacenter.

In his pre-briefing Aylor said, “[The multi-generational partnership that we have around seven nanometer [is] a key catalyst for us having this leadership capability in terms of cache density, in terms of core density, and a very compelling level performance. You will hear from TSMC that they have a full commitment and full capability to ramp the volumes that are needed in the market. They believe in the technology so much that they will actually be deploying it in their datacenter. So, TSMC will also talk about how they are now deploying Epyc second generation Rome in their data center for virtualization environments for EDA deployments.”

Let the good time roll for now.

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