Intel Debuts New GPU – Ponte Vecchio – and Outlines Aspirations for oneAPI

By John Russell

November 17, 2019

Intel today revealed a few more details about its forthcoming Xe line of GPUs – the top SKU is named Ponte Vecchio and will be used in Aurora, the first planned U.S. exascale computer. Intel also provided a glimpse of Aurora’s basic node which will feature two Xeons and six Ponte Vecchios. Intel also took time to dig deeper into its oneAPI effort which is now in “beta launch” and positioned as both an industry initiative and an Intel product intended to enhance development for heterogeneous compute architectures.

The announcements came at Intel’s HPC Developer Conference running today and tomorrow in Denver, almost literally next door to SC19 at the Denver Convention Center, and in a media pre-briefing last week led by Intel’s Raj Hazra, VP & GM for enterprise and government. At the pre-briefing, Hazra fleshed out Intel’s vision for converged HPC-AI and described Intel’s developing “XPU” strategy which embraces CPUs, GPUs, FPGAs, NNP (neural net processors), and other accelerators as necessary elements for advancing computing on all fronts from high-end HPC to small power hungry edge devices.

“No longer [does] one size fit all,” said Hazra. “We have to look at architectures tuned to the needs of varying kinds of workloads in this convergence era.” Citing a 60 percent CAGR for MIPS, Hazra said Intel now needed “a portfolio of architectures” to address compute needs, which he labelled as Intel’s XPU approach.

Relatively few technical details about the Xe were discussed. It will use Intel’s new 7nm process technology, Foveros multi-die packaging, and be ready to use Intel-backed CXL interconnect technology. Ari Rauch, Intel GM visual technology team and graphics business, was coy when asked if Ponte Vecchio would use Intel’s nascent EMIB (embedded multi connect bridge) technology. “We’re not disclosing [that] but you can assume the device is taking into advantage all the latest and greatest technology from Intel …3D packaging, memory technology, they’re all in play.” Later at the DevCon, Intel confirmed the use of EMIB.

He did say Intel was focused on having a common over-arching architecture and common programming model across the Xe line, but in the context of also delivering ‘microarchitectures’ targeting specific workloads. One can imagine a variety of memory, IO, and mixed precision, and power consumption attributes delivered in members of the Xeline. The first Ponte Vecchio devices to market will presumably be in Aurora which is due in 2021. Intel confirmed it planned to sell Xe GPUs as standalone products although with few details and no firm timeline. In fact, the first-to-market Xe device will appear in 2020 and be in a consumer setting according to Intel.

Intel was likewise scant with new details about Aurora which will be located at Argonne National Laboratory. Hazra reiterated Aurora would have more than 200 racks, 230 petabytes of storage, and more than 10 petabytes of memory. The two CPUs on each node will be Sapphire Rapids generation Xeons connected to six Ponte Vecchios and be programmed with Intel’s oneAPI stack.

When asked, Raj declined to say what the rack type would be or to specify the ratio of DDR5 to Optane memory planned. “We will be taking the covers off gradually over the next few months, and we will get to those levels of specific configuration details at that point,” he said. (Interestingly, from a macro level an Aurora node looks a lot like a Summit node – of course the devil is in the details.)

Bill Savage, GM for compute performance and developer products, provided a fair amount of detail around oneAPI which is now available on Intel’s DevCloud. Intel describes oneAPI as a unified programming model to simplify development across diverse architectures.

Savage noted developers generally rely on abstractions to get access to hardware through middleware and frameworks, and in the case of HPC, by coding more closely and directly to the hardware. Targeting new architectures typically requires low level programming and sometimes different programming languages and libraries. The same can said for middleware and frameworks often optimized for specific hardware. Savage pointed to TensorFlow which when first released was “optimized for one vendor’s GPU” and not for anything else.”

The oneAPI vision is expansive. It would offer a “low level common interface to heterogeneous hardware so that HPC developers can code directly to the hardware, through languages and libraries that are shared across architectures and across vendors as well as making sure that middleware and frameworks are powered by one API and fully optimized for the developers that live on top of abstractions.” That seems a worthy idea but a tall order.

Here is Savage on oneAPI and on the decision to create Data Parallel C++ (DPC++) as the base language:

“It is both an industry initiative and an Intel product. [The] industry initiative is driving an open standard with an open source reference implementation with partners in the industry. [By doing this] we can share and reuse source code across architectures and vendors.

“We looked closely at OpenCL, Java and other languages, and how they had compromises in performance or delivered reuse of software. [We] selected a language that could deliver both the productivity and performance. It’s C++ based but has we’ve applied a number extensions to make it more usable, and developer friendly as well as deliver better performance. Then we added a set of APIs for low level libraries to offer a common set of capabilities across the domains of HPC and AI, as well as other domains at the low level. So those are parts of the standard.”

The Intel oneAPI product has a few additional features including a compatibility tool and some analysis and debug tools.

“We have an implementation of the data parallel C++ compiler as well as the set of libraries that match the APIs in the specification. So that’s the core of the Intel one API product. In addition, we took our analysis tools like the VTune Inspector/Advisor, and we’ve enabled those for one API as well debugging and supporting tools,” said Savage.

Intel also developed compatibility tool to aid in source code migration such as Cuda to DPC++. “We get the source in our data parallel C++ that can cross architecture and vendor boundaries and you should get good performance in the first port,” said Savage. He expects tuning for specific microarchitectures will be required to achieve optimum performance.

A big question is who is supporting the effort. At the media pre-briefing Intel promised more information on partners and organization of the initiative would be forthcoming during its developer conference now underway.

Lastly, lest you think the venerable Xeon is being lost in the shuffle of Intel’s emerging XPUs approach, Hazra called it the workhorse of Intel’s converged HPC/AI strategy. As shown below nothing really new about Intel’s CPU roadmap was presented but Hazra emphasized previously discussed plans particularly the addition of mixed-precision capabilities in forthcoming generations.

“We’re shipping our Cascade Lake 14 nanometer processor today with Intel DL Boost, which is also called VNNI (vector neural net instructions), and [it’s] enabled with Optane Datacenter Persistent Memory first generation. That beat continues in 2020 as we introduce Cooper Lake with the next generation of DL Boost and specifically bringing bfloat16, the industry’s converged reduced precision, numeric format for AI into the processor for the first time.”

The 10nm Ice Lake ramp-up continues in the second half of 2020 and will provide more microarchitecture and architectural features for both traditional HPC and AI, said Hazra. Sapphire Rapids, of course, is due in 2021 in time for Aurora. Hazra said little about it beyond it would have impressive scale-out and scale-up performance.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Graphcore Introduces Next-Gen Intelligence Processing Unit for AI Workloads

July 15, 2020

British hardware designer Graphcore, which emerged from stealth in 2016 to launch its first-generation Intelligence Processing Unit (IPU), has announced its next-generation IPU platform: the IPU-Machine M2000. With the n Read more…

By Oliver Peckham

heFFTe: Scaling FFT for Exascale

July 15, 2020

Exascale computing aspires to provide breakthrough solutions addressing today’s most critical challenges in scientific discovery, energy assurance, economic competitiveness, and national security. This has been the mai Read more…

By Jack Dongarra and Stanimire Tomov

There’s No Storage Like ATGC: Breakthrough Helps to Store ‘The Wizard of Oz’ in DNA

July 15, 2020

Even as storage density reaches new heights, many researchers have their eyes set on a paradigm shift in high-density information storage: storing data in the four nucleotides (A, T, G and C) that constitute DNA, a metho Read more…

By Oliver Peckham

Get a Grip: Intel Neuromorphic Chip Used to Give Robotics Arm a Sense of Touch

July 15, 2020

Moving neuromorphic technology from the laboratory into practice has proven slow-going. This week, National University of Singapore researchers moved the needle forward demonstrating an event-driven, visual-tactile perce Read more…

By John Russell

What’s New in HPC Research: Volcanoes, Mobile Games, Proteins & More

July 14, 2020

In this bimonthly feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here. Read more…

By Oliver Peckham

AWS Solution Channel

INEOS TEAM UK Accelerates Boat Design for America’s Cup Using HPC on AWS

The America’s Cup Dream

The 36th America’s Cup race will be decided in Auckland, New Zealand in 2021. Like all the teams, INEOS TEAM UK will compete in a boat whose design will have followed guidelines set by race organizers to ensure the crew’s sailing skills are fully tested. Read more…

Intel® HPC + AI Pavilion

Supercomputing the Pandemic: Scientific Community Tackles COVID-19 from Multiple Perspectives

Since their inception, supercomputers have taken on the biggest, most complex, and most data-intensive computing challenges—from confirming Einstein’s theories about gravitational waves to predicting the impacts of climate change. Read more…

Joliot-Curie Supercomputer Used to Build First Full, High-Fidelity Aircraft Engine Simulation

July 14, 2020

When industrial designers plan the design of a new element of a vehicle’s propulsion or exterior, they typically use fluid dynamics to optimize airflow and increase the vehicle’s speed and efficiency. These fluid dyn Read more…

By Oliver Peckham

Graphcore Introduces Next-Gen Intelligence Processing Unit for AI Workloads

July 15, 2020

British hardware designer Graphcore, which emerged from stealth in 2016 to launch its first-generation Intelligence Processing Unit (IPU), has announced its nex Read more…

By Oliver Peckham

heFFTe: Scaling FFT for Exascale

July 15, 2020

Exascale computing aspires to provide breakthrough solutions addressing today’s most critical challenges in scientific discovery, energy assurance, economic c Read more…

By Jack Dongarra and Stanimire Tomov

Get a Grip: Intel Neuromorphic Chip Used to Give Robotics Arm a Sense of Touch

July 15, 2020

Moving neuromorphic technology from the laboratory into practice has proven slow-going. This week, National University of Singapore researchers moved the needle Read more…

By John Russell

Max Planck Society Begins Installation of Liquid-Cooled Supercomputer from Lenovo

July 9, 2020

Lenovo announced today that it is supplying a new high performance computer to the Max Planck Society, one of Germany's premier research organizations. Comprise Read more…

By Tiffany Trader

President’s Council Targets AI, Quantum, STEM; Recommends Spending Growth

July 9, 2020

Last week the President Council of Advisors on Science and Technology (PCAST) met (webinar) to review policy recommendations around three sub-committee reports: Read more…

By John Russell

Google Cloud Debuts 16-GPU Ampere A100 Instances

July 7, 2020

On the heels of the Nvidia’s Ampere A100 GPU launch in May, Google Cloud is announcing alpha availability of the A100 “Accelerator Optimized” VM A2 instance family on Google Compute Engine. The instances are powered by the HGX A100 16-GPU platform, which combines two HGX A100 8-GPU baseboards using... Read more…

By Tiffany Trader

Q&A: HLRS’s Bastian Koller Tackles HPC and Industry in Germany and Europe

July 6, 2020

In this exclusive interview for HPCwire – sadly not face to face – Steve Conway, senior advisor for Hyperion Research, talks with Dr.-Ing Bastian Koller about the state of HPC and its collaboration with Industry in Europe. Koller is a familiar figure in HPC. He is the managing director at High Performance Computing Center Stuttgart (HLRS) and also serves... Read more…

By Steve Conway, Hyperion

OpenPOWER Reboot – New Director, New Silicon Partners, Leveraging Linux Foundation Connections

July 2, 2020

Earlier this week the OpenPOWER Foundation announced the contribution of IBM’s A21 Power processor core design to the open source community. Roughly this time Read more…

By John Russell

Supercomputer Modeling Tests How COVID-19 Spreads in Grocery Stores

April 8, 2020

In the COVID-19 era, many people are treating simple activities like getting gas or groceries with caution as they try to heed social distancing mandates and protect their own health. Still, significant uncertainty surrounds the relative risk of different activities, and conflicting information is prevalent. A team of Finnish researchers set out to address some of these uncertainties by... Read more…

By Oliver Peckham

[email protected] Turns Its Massive Crowdsourced Computer Network Against COVID-19

March 16, 2020

For gamers, fighting against a global crisis is usually pure fantasy – but now, it’s looking more like a reality. As supercomputers around the world spin up Read more…

By Oliver Peckham

[email protected] Rallies a Legion of Computers Against the Coronavirus

March 24, 2020

Last week, we highlighted [email protected], a massive, crowdsourced computer network that has turned its resources against the coronavirus pandemic sweeping the globe – but [email protected] isn’t the only game in town. The internet is buzzing with crowdsourced computing... Read more…

By Oliver Peckham

Supercomputer Simulations Reveal the Fate of the Neanderthals

May 25, 2020

For hundreds of thousands of years, neanderthals roamed the planet, eventually (almost 50,000 years ago) giving way to homo sapiens, which quickly became the do Read more…

By Oliver Peckham

DoE Expands on Role of COVID-19 Supercomputing Consortium

March 25, 2020

After announcing the launch of the COVID-19 High Performance Computing Consortium on Sunday, the Department of Energy yesterday provided more details on its sco Read more…

By John Russell

Neocortex Will Be First-of-Its-Kind 800,000-Core AI Supercomputer

June 9, 2020

Pittsburgh Supercomputing Center (PSC - a joint research organization of Carnegie Mellon University and the University of Pittsburgh) has won a $5 million award Read more…

By Tiffany Trader

Honeywell’s Big Bet on Trapped Ion Quantum Computing

April 7, 2020

Honeywell doesn’t spring to mind when thinking of quantum computing pioneers, but a decade ago the high-tech conglomerate better known for its control systems waded deliberately into the then calmer quantum computing (QC) waters. Fast forward to March when Honeywell announced plans to introduce an ion trap-based quantum computer whose ‘performance’ would... Read more…

By John Russell

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

By Doug Black

Leading Solution Providers

Contributors

Nvidia’s Ampere A100 GPU: Up to 2.5X the HPC, 20X the AI

May 14, 2020

Nvidia's first Ampere-based graphics card, the A100 GPU, packs a whopping 54 billion transistors on 826mm2 of silicon, making it the world's largest seven-nanom Read more…

By Tiffany Trader

‘Billion Molecules Against COVID-19’ Challenge to Launch with Massive Supercomputing Support

April 22, 2020

Around the world, supercomputing centers have spun up and opened their doors for COVID-19 research in what may be the most unified supercomputing effort in hist Read more…

By Oliver Peckham

Australian Researchers Break All-Time Internet Speed Record

May 26, 2020

If you’ve been stuck at home for the last few months, you’ve probably become more attuned to the quality (or lack thereof) of your internet connection. Even Read more…

By Oliver Peckham

15 Slides on Programming Aurora and Exascale Systems

May 7, 2020

Sometime in 2021, Aurora, the first planned U.S. exascale system, is scheduled to be fired up at Argonne National Laboratory. Cray (now HPE) and Intel are the k Read more…

By John Russell

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

TACC Supercomputers Run Simulations Illuminating COVID-19, DNA Replication

March 19, 2020

As supercomputers around the world spin up to combat the coronavirus, the Texas Advanced Computing Center (TACC) is announcing results that may help to illumina Read more…

By Staff report

$100B Plan Submitted for Massive Remake and Expansion of NSF

May 27, 2020

Legislation to reshape, expand - and rename - the National Science Foundation has been submitted in both the U.S. House and Senate. The proposal, which seems to Read more…

By John Russell

John Martinis Reportedly Leaves Google Quantum Effort

April 21, 2020

John Martinis, who led Google’s quantum computing effort since establishing its quantum hardware group in 2014, has left Google after being moved into an advi Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This