SiFive Accelerates Chip Design with Cloud Tools

By George Leopold

March 25, 2020

Chip designers are drawing on new cloud resources along with conventional electronic design automation (EDA) tools to accelerate IC templates from tape-out to custom silicon.

Among the challengers to chip design leader Arm is SiFive. The IC design work-flow startup said this week it is combining design and verification tools from EDA leader Synopsys with the Microsoft Azure cloud. The result will be a platform engineering framework running in SiFive’s 16 design centers around the world.

The RISC-V startup based in San Mateo, Calif., said the EDA tool-cloud combination would help it further reduce the time, complexity and cost of custom silicon. “By collaborating with Synopsys and leveraging Microsoft Azure, SiFive is improving its portfolio of design tools,” the company said Wednesday (March 25).

Chris Lattner, SiFive’s senior vice president for platform engineering, said cloud-based EDA tools coupled with intellectual property building blocks promise to accelerate custom silicon designs at a rate approaching that of software development.

A target market for cloud-based chip design is silicon accelerators used for machine learning inference. Those hardware accelerators are often used with graphics processors to speed up model training and inference. The market for deep learning devices that can process data at the network edge is expected to explode over the next few years.

“On-device decisions drive new design requirements for the core, cache, memory and processing offload accelerators used inside the silicon,” Lattern noted in a blog post announcing SiFive’s cloud-based tools. “An agile, scalable, programmatic approach to SoC design is required to create domain-specific accelerators and bring them to market quickly.”

SiFive is among a growing roster of chip design startups coalescing around the open standard RISC-V instruction set and associated intellectual property. The startup’s web-based tool is designed to quickly configure processor cores based on RISC-V. Last year, its cloud-based framework was used to tape out its 64-bit RISC-V Linux chip.

Having demonstrated its quick-turnaround chip design capability, Lattner said SiFive is concentrating its cloud-based methodology on “domain-specific” workloads, including accelerator designs. The goal is providing custom silicon that can adapt to “shifting workloads,” Lattner added.

Customers and investors are paying attention as SiFive emerges as a challenger to chip IP leader Arm. The startup was founded in 2015 by the inventors of the reduced instruction set computing framework. Among SiFive’s key investors are Intel Capital and Qualcomm. The latter is a founding member of the RISC-V Foundation. The wireless chip maker was an early Arm customer.

SiFive has so far raised more than $129 million in four funding rounds. The Silicon Valley startup has design facilities in: Beaverton, Ore., near Intel’s Hillsboro campus; Austin, Texas; Boston; Bangalore and Pune, India; Shanghai; the global chip manufacturing hub in Hsinchu, Taiwan; and Seoul, South Korea.

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