The U.S. military is ramping up efforts to secure semiconductors and its electronics supply chain by embedding defenses during the chip design phase. The automation effort also addresses the high cost and complexity of securing hardware development along with current lack of secure-oriented chip design tools.

The Defense Advanced Research Projects Agency (DARPA) announced a pair of teams this week to ramp up its secure chip design initiative. The year-old Automatic Implementation of Secure Silicon (AISS) program also would help silicon architectures specify performance constraints while automating the design-in of defenses that would secure an entire device lifecycle.

The teams led by EDA tool specialist Synopsys and Northrop Grumman will develop Arm-based architectures that incorporate a “security engine” used to defend against attacks and supply chain threats such as reverse engineering of chips. An upgradeable platform would provide the infrastructure that military planners say is needed to manage hardened chips from deployment to scrapheap.

Launched in April 2019, AISS is designed to balance security and economic considerations in protecting the IC design process as well as chip supply chains.

Besides Arm, the Synopsys team includes aerospace giant Boeing, the University of Florida’s Institute for Cybersecurity, Texas A&M University, University of California at San Diego and U.K.-based embedded analytics vendor UltraSoC.

Northrop Grumman heads a team that includes IBM, University of Arkansas and University of Florida.

Competing “security engine” approaches would address chip vulnerabilities such as side channel attacks, hardware Trojans, reverse engineering and supply chain exploits. Side channel attacks include tracking device power consumption as a means of stealing an encryption key.

In a later phase, the Synopsys team will seek to leverage EDA tools to integrate its security engine into SoC platforms. The approach would combine “security-aware” EDA tools developed under the DARPA program using commercial intellectual property from Arm, Synopsys and UltraSoC.

Chip designers would then specify key constraints for power, area, speed and security for AISS tools. Those tools would then “automatically generate optimal implementations based on the application objectives,” program officials said.

“The ultimate goal of the AISS program is to accelerate the timeline from architecture to security-hardened [register transfer level] from one year, to one week—and to do so at a substantially reduced cost,” said Serge Leef, the DARPA’s program manager for AISS.

AISS seeks to automate the process of integrating “scalable defense mechanisms” into chip designs. That automation capability, the agency added, would help designers determine the tradeoffs between cost and security while boosting productivity.

Among the drivers of the chip design effort is the proliferation of Internet of Things devices. Unsecured chips have become an inviting target for hackers probing for chip vulnerabilities at the network edge. At the same time, deployment of embedded countermeasures has been slowed by cost, complexity and a lack of security-oriented design tools, DARPA noted. Those tools also must to be integrated with semiconductor IP, including designs by chip intellectual property vendors such as Arm.