DDR5 Memory Spec Doubles Data Rate, Quadruples Density

By Tiffany Trader

July 16, 2020

Standards group JEDEC announced the publication of the DDR5 SDRAM spec, the next-generation standard for random access memory (RAM). Compared to DDR4, the DDR5 spec delivers twice the performance and improved power efficiency, addressing ever-growing demand from datacenter and cloud environments, as well as artificial intelligence and HPC applications.

Providing up to 6.4 Gbps, DDR5 doubles the bandwidth of its predecessor, DDR4, which tops out at 3.2 Gpbs. At launch, DDR5 modules will reach 4.8 Gbps, providing a 50 percent improvement versus the previous generation. Density goes up four-fold with maximum density increasing from 16 Gigabits per die to 64 Gigabits per die in the new spec. JEDEC representatives indicated there will be both 8 Gigabit and 16 Gigabit DDR5 products at launch.

DDR5 boosts signaling rates to 6,400 MT/s, but Desi Rhoden, chairman, JEDEC JC-42 memory committee, and executive vice president of Montage Technology, says there are discussions about going beyond that. “I think you can expect that you might see something above that as well — and much improved channel utilization,” he said in a press briefing held earlier this week.

DDR DRAM Generational Evolution (Source: JEDEC)

A new feature, Decision Feedback Equalization, was added to improve IO speed scalability. “It enables us to build really high frequency interfaces,” said Rhoden. “We didn’t need this before because we were at performances that did not demand it, but now we have to use equalization to get to the high speed IO. And this is the first time we’ve ever had it in the DRAM itself. We’ve had it in support logic before but the first time in the DRAM itself.”

A fine grain refresh feature, all bank refresh, improves 16 Gigabit device latency. Same bank refresh offers the ability to refresh in one part of the die while other parts are in use, providing higher utilization.

Additional features/specs include:

• On-die ECC and other scaling features enable manufacturing on advanced process nodes.
• Improved power efficiency enabled by Vdd going from 1.2V to 1.1V as compared to DDR4.
• Use of the MIPI Alliance I3C Basic specification for system management bus.
• At the module level, voltage regulator on DIMM design enables pay as you go scalability, better voltage tolerance for improved DRAM yields and the potential to further reduce power consumption.
• The DIMM has two 40-bit (32 data bits plus eight ECC bits) independent sub-channels on the same module for efficiency and improved reliability.

The DDR5 spec also increases stacking capability, doubling the height from the previous generation. “The DDR4 spec defines up to an 8-high stack, and for most of the industry the maximum stack height was 4-high. For DDR5, we have defined up to a 16-high stack, and expect up to 8-high stack products,” said Johnny Kim, chairman, JEDEC JC-42.3C subcommittee and staff engineer, memory product planning and enabling at Samsung.

With a DDR5 DIMM supporting 40 placements of DRAM, an 8-high stack at 64 gigabits per die brings the upper capacity to 2 terabytes.

Devices are sampling now and CPUs are available to work with them, JEDEC said. Historically, it’s taken about 18 months to transition from one generation to the next and the JEDEC representatives expect that trend to hold with the server market leading. “The server datacenter market led for the transition to DDR4 back in 2014, and the datacenter market has grown substantially since that time. So we think that that’ll [even more so] be the snowplow for DDR5 adoption,” said Paul Fahey, JEDEC board of directors and vice president DRAM technology at SK hynix.

The previous two DDR generations have come at about a seven-year cadence, and this longevity, along with the demands of the data age, set a high bar for the DDR5 spec and roadmap. “These generations always live longer than initially anticipate them to live,” said Rhoden. “DDR5, because it does have so much capability built into it, has the potential to live quite a long life.”

“We added a lot into the spec to give it that longevity,” noted Frank Ross, JEDEC board of directors and senior member of technical staff, lead architect, Micron. “Whether we use all of those features and all of the capacities and so forth is yet to be seen. But we’ve seen each subsequent DRAM generation last longer than previous one as new applications come around. We’ve improved DRAM reliability quite a bit over the years. You have applications that will continue to use DDR3 and DDR4 for a long time, and I imagine DDR5 will be the same.”

Going forward though, the expectation is that all new designs will be focused on the newest standard. “To take advantage of the kinds of things that DDR5 offers, I think people will be wanting to design in it and as quickly as possible,” said Ross.

“We’ve got probably the best standard we’ve ever produced,” Ross added. “I think the industry is going to be very impressed. And everyone has to remember, DDR5 is a system level solution. So we’re producing a component spec at the same time we’re producing a module spec, as well as support components. So there’s just a tremendous amount of work that goes into the spec and in the end, we have an extremely high quality document.”

Over 150 companies were involved in the creation of this spec. Micron, Samsung, SK hynix, Synopsys, Intel and AMD are among the companies expressing their support and engagement.

Micron Technology, which announced DDR5 RDIMM samples in January (2020), is now launching an enablement program to provide early access to technical resources, products and ecosystem partners. The program will aid in the design, development and qualification of next-generation computing platforms that use DDR5, said Mircon.

SK Hynix has been working on DDR5 samples since 2018, and expects to start mass manufacturing by the end of this year.

Synopsys introduced the industry’s first JEDEC DDR5 compliant Verification IP (VIP) for DDR5 DRAM/DIMM to enable the design and verification of next-generation memory devices.

The DDR5 SDRAM (JESD79-5) spec document is available for download from the JEDEC website.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

University of Chicago Researchers Generate First Computational Model of Entire SARS-CoV-2 Virus

January 15, 2021

Over the course of the last year, many detailed computational models of SARS-CoV-2 have been produced with the help of supercomputers, but those models have largely focused on critical elements of the virus, such as its Read more…

By Oliver Peckham

Pat Gelsinger Returns to Intel as CEO

January 14, 2021

The Intel board of directors has appointed a new CEO. Intel alum Pat Gelsinger is leaving his post as CEO of VMware to rejoin the company that he parted ways with 11 years ago. Gelsinger will succeed Bob Swan, who will remain CEO until Feb. 15. Gelsinger previously spent 30 years... Read more…

By Tiffany Trader

Roar Supercomputer to Support Naval Aircraft Research

January 14, 2021

One might not think “aircraft” when picturing the U.S. Navy, but the military branch actually has thousands of aircraft currently in service – and now, supercomputing will help future naval aircraft operate faster, Read more…

By Staff report

DOE and NOAA Extend Computing Partnership, Plan for New Supercomputer

January 14, 2021

The National Climate-Computing Research Center (NCRC), hosted by Oak Ridge National Laboratory (ORNL), has been supporting the climate research of the National Oceanic and Atmospheric Administration (NOAA) for the last 1 Read more…

By Oliver Peckham

Using Micro-Combs, Researchers Demonstrate World’s Fastest Optical Neuromorphic Processor for AI

January 13, 2021

Neuromorphic computing, which uses chips that mimic the behavior of the human brain using virtual “neurons,” is growing in popularity thanks to high-profile efforts from Intel and others. Now, a team of researchers l Read more…

By Oliver Peckham

AWS Solution Channel

Now Available – Amazon EC2 C6gn Instances with 100 Gbps Networking

Amazon EC2 C6gn instances powered by AWS Graviton2 processors are now available!

Compared to C6g instances, this new instance type provides 4x higher network bandwidth, 4x higher packet processing performance, and 2x higher EBS bandwidth. Read more…

Intel® HPC + AI Pavilion

Intel Keynote Address

Intel is the foundation of HPC – from the workstation to the cloud to the backbone of the Top500. At SC20, Intel’s Trish Damkroger, VP and GM of high performance computing, addresses the audience to show how Intel and its partners are building the future of HPC today, through hardware and software technologies that accelerate the broad deployment of advanced HPC systems. Read more…

Honing In on AI, US Launches National Artificial Intelligence Initiative Office

January 13, 2021

To drive American leadership in the field of AI into the future, the National Artificial Intelligence Initiative Office has been launched by the White House Office of Science and Technology Policy (OSTP). The new agen Read more…

By Todd R. Weiss

Pat Gelsinger Returns to Intel as CEO

January 14, 2021

The Intel board of directors has appointed a new CEO. Intel alum Pat Gelsinger is leaving his post as CEO of VMware to rejoin the company that he parted ways with 11 years ago. Gelsinger will succeed Bob Swan, who will remain CEO until Feb. 15. Gelsinger previously spent 30 years... Read more…

By Tiffany Trader

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

Intel ‘Ice Lake’ Server Chips in Production, Set for Volume Ramp This Quarter

January 12, 2021

Intel Corp. used this week’s virtual CES 2021 event to reassert its dominance of the datacenter with the formal roll out of its next-generation server chip, the 10nm Xeon Scalable processor that targets AI and HPC workloads. The third-generation “Ice Lake” family... Read more…

By George Leopold

Researchers Say It Won’t Be Possible to Control Superintelligent AI

January 11, 2021

Worries about out-of-control AI aren’t new. Many prominent figures have suggested caution when unleashing AI. One quote that keeps cropping up is (roughly) th Read more…

By John Russell

AMD Files Patent on New GPU Chiplet Approach

January 5, 2021

Advanced Micro Devices is accelerating the GPU chiplet race with the release of a U.S. patent application for a device that incorporates high-bandwidth intercon Read more…

By George Leopold

Programming the Soon-to-Be World’s Fastest Supercomputer, Frontier

January 5, 2021

What’s it like designing an app for the world’s fastest supercomputer, set to come online in the United States in 2021? The University of Delaware’s Sunita Chandrasekaran is leading an elite international team in just that task. Chandrasekaran, assistant professor of computer and information sciences, recently was named... Read more…

By Tracey Bryant

Intel Touts Optane Performance, Teases Next-gen “Crow Pass”

January 5, 2021

Competition to leverage new memory and storage hardware with new or improved software to create better storage/memory schemes has steadily gathered steam during Read more…

By John Russell

Farewell 2020: Bleak, Yes. But a Lot of Good Happened Too

December 30, 2020

Here on the cusp of the new year, the catchphrase ‘2020 hindsight’ has a distinctly different feel. Good riddance, yes. But also proof of science’s power Read more…

By John Russell

Esperanto Unveils ML Chip with Nearly 1,100 RISC-V Cores

December 8, 2020

At the RISC-V Summit today, Art Swift, CEO of Esperanto Technologies, announced a new, RISC-V based chip aimed at machine learning and containing nearly 1,100 low-power cores based on the open-source RISC-V architecture. Esperanto Technologies, headquartered in... Read more…

By Oliver Peckham

Azure Scaled to Record 86,400 Cores for Molecular Dynamics

November 20, 2020

A new record for HPC scaling on the public cloud has been achieved on Microsoft Azure. Led by Dr. Jer-Ming Chia, the cloud provider partnered with the Beckman I Read more…

By Oliver Peckham

NICS Unleashes ‘Kraken’ Supercomputer

April 4, 2008

A Cray XT4 supercomputer, dubbed Kraken, is scheduled to come online in mid-summer at the National Institute for Computational Sciences (NICS). The soon-to-be petascale system, and the resulting NICS organization, are the result of an NSF Track II award of $65 million to the University of Tennessee and its partners to provide next-generation supercomputing for the nation's science community. Read more…

Is the Nvidia A100 GPU Performance Worth a Hardware Upgrade?

October 16, 2020

Over the last decade, accelerators have seen an increasing rate of adoption in high-performance computing (HPC) platforms, and in the June 2020 Top500 list, eig Read more…

By Hartwig Anzt, Ahmad Abdelfattah and Jack Dongarra

Aurora’s Troubles Move Frontier into Pole Exascale Position

October 1, 2020

Intel’s 7nm node delay has raised questions about the status of the Aurora supercomputer that was scheduled to be stood up at Argonne National Laboratory next year. Aurora was in the running to be the United States’ first exascale supercomputer although it was on a contemporaneous timeline with... Read more…

By Tiffany Trader

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

By Doug Black

Programming the Soon-to-Be World’s Fastest Supercomputer, Frontier

January 5, 2021

What’s it like designing an app for the world’s fastest supercomputer, set to come online in the United States in 2021? The University of Delaware’s Sunita Chandrasekaran is leading an elite international team in just that task. Chandrasekaran, assistant professor of computer and information sciences, recently was named... Read more…

By Tracey Bryant

Leading Solution Providers

Contributors

Top500: Fugaku Keeps Crown, Nvidia’s Selene Climbs to #5

November 16, 2020

With the publication of the 56th Top500 list today from SC20's virtual proceedings, Japan's Fugaku supercomputer – now fully deployed – notches another win, Read more…

By Tiffany Trader

Texas A&M Announces Flagship ‘Grace’ Supercomputer

November 9, 2020

Texas A&M University has announced its next flagship system: Grace. The new supercomputer, named for legendary programming pioneer Grace Hopper, is replacing the Ada system (itself named for mathematician Ada Lovelace) as the primary workhorse for Texas A&M’s High Performance Research Computing (HPRC). Read more…

By Oliver Peckham

At Oak Ridge, ‘End of Life’ Sometimes Isn’t

October 31, 2020

Sometimes, the old dog actually does go live on a farm. HPC systems are often cursed with short lifespans, as they are continually supplanted by the latest and Read more…

By Oliver Peckham

Nvidia and EuroHPC Team for Four Supercomputers, Including Massive ‘Leonardo’ System

October 15, 2020

The EuroHPC Joint Undertaking (JU) serves as Europe’s concerted supercomputing play, currently comprising 32 member states and billions of euros in funding. I Read more…

By Oliver Peckham

Gordon Bell Special Prize Goes to Massive SARS-CoV-2 Simulations

November 19, 2020

2020 has proven a harrowing year – but it has produced remarkable heroes. To that end, this year, the Association for Computing Machinery (ACM) introduced the Read more…

By Oliver Peckham

Nvidia-Arm Deal a Boon for RISC-V?

October 26, 2020

The $40 billion blockbuster acquisition deal that will bring chipmaker Arm into the Nvidia corporate family could provide a boost for the competing RISC-V architecture. As regulators in the U.S., China and the European Union begin scrutinizing the impact of the blockbuster deal on semiconductor industry competition and innovation, the deal has at the very least... Read more…

By George Leopold

Intel Xe-HP GPU Deployed for Aurora Exascale Development

November 17, 2020

At SC20, Intel announced that it is making its Xe-HP high performance discrete GPUs available to early access developers. Notably, the new chips have been deplo Read more…

By Tiffany Trader

HPE, AMD and EuroHPC Partner for Pre-Exascale LUMI Supercomputer

October 21, 2020

Not even a week after Nvidia announced that it would be providing hardware for the first four of the eight planned EuroHPC systems, HPE and AMD are announcing a Read more…

By Oliver Peckham

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This