A Declaration of Interdependence through Non von Neumann Architecture

By Thomas Sterling, Indiana University

July 22, 2020

Editor’s note: Where does computing architecture go from here? That’s an ambitious question for sure, perhaps overly ambitious, but tackling ambitious ideas has been the habit of Thomas Sterling, Professor of Intelligent Systems Engineering at the Indiana University (IU) School of Informatics, Computing, and Engineering. In this first of two contributed pieces, Sterling examines the early strengths and later inhibiting consequences of settling on von Neumann architecture (vNa), which for years fueled spectacular growth but now has become a roadblock. The ALU is king in vNa and maximizing its use is the driving principle. Sterling looks at why that thinking no longer holds. In his second article Sterling will examine alternative directions to push past vNa into various Non von Neumann architectures. Enjoy.

The unprecedented success of the von Neumann architecture (vNa) and its many derivatives over the last seven decades has yielded a performance-gain in excess of ten trillion-fold exceeding the progress of any other technology in human history by orders of magnitude. The abstract vNa has become the integral aspect of the HPC corporate mentality that it serves as the standard for general-purpose computing with all other forms of structures relegated to “special purpose,” “domain specific,” “accelerators,” “GPUs,” and others.

In addition to the elegance and simplicity of vNa, it was also of true practical value serving as a template for the organization and semantics of digital electronics hardware to be fabricated not only with the enabling technologies of that era (circa 1950) but also across a succession of technology advances for decades beyond. This suitability to effectively leverage the functionality and capability of available underlying device types is a major factor in the past success of vNa. However, this is not only no longer the case, it is in increasing conflict with ability to optimize the use of contemporary and future semiconductor technologies that must drive a much-needed architecture transformation to extend the efficiency and scalability of future generation HPC systems. This first of two articles describes the poor fit of the original vNa concepts to the current semiconductor enabling technologies at the end of Moore’s law and practical power constraints. The constructive contribution of this is the exposure and identification of intrinsic latent opportunities for dramatic improvements in performance. Through relaxation of limiting properties imposed by the assumption of vNa family of execution models, semantics, and structures, a leap in future performance of HPC may yet be gained. The second article, at the discretion of HPCwire, will suggest aspects of Non von Neumann architectures (NvNa), some already in consideration or even employed, that can exploit these opportunities recognizing that there is not only one answer, nor any one answer that fully addresses all needs and choices.

John von Neumann in the 1940s (Wikimedia Commons)

The most pernicious of the legacy factors implicit in the classical von Neumann architecture is its fundamental objective function; that is its choice of resource considered as precious and for which the resulting designs are optimized. Sophisticated designs attempt to devise “balanced architectures” mixing investment of resources to a multi-dimensional “best” including normalizing factors such as cost, area, or energy consumption. But at the risk of over-simplifying, historically the precious resource of vNa derivatives is the rate of performing numeric operations, often more specifically the floating-point throughput. This is certainly reflected by the HPC community adoption of the HPL (High-Performance Linpack) benchmark which measures the floating-point performance of a specific dense-matrix algorithm dominated by double precision floating-point addition and multiplication operations, Rmax. John von Neumann and his University of Pennsylvania colleagues J. Presper Eckert and John Mauchly recognized, chiefly through their experiences in the development of ENIAC by the US Army, that the arithmetic logic unit (ALU) was among the most complicated and component-intensive elements of a digital electronic calculating engine possibly making it the most expensive and motivating treating it as the critical-path element of the vNa. Although memory might have also been considered as the pacing item (and was in many ways), the focus reasonably remained on logic.

Through the technology generations of 1) vacuum tubes, 2) germanium transistors, 3) silicon transistors, 4) SSI and 5) MSI, the large ALUs and FPUs dominated the architecture design based on the traditional vNa concepts even as innovative structures such as pipelining for execution and floating point, locality based caches, speculative actions such as branch prediction, introduction of virtual memory with TLBs, register banks, Tomasulo-based reservation stations, and other creative optimizations advanced the state-of-the-art dramatically from its incipient implementations such as Cambridge EDSAC, MIT Whirlwind, and the ERA 1101. But at all times, arithmetic performance was supported by the rest of the processor architecture. By the early years of the 21st century, the balance of die area was shifting as the feature-size improved exponentially. The actual arithmetic units became an ever-decreasing proportion of the overall processor core die area. Yet, in accordance with tradition, the majority of the die was dedicated to support the throughput of the minority of the die allocated to the FPU. This upside-down optimization continues to stress FPU utilization at the cost (in area) of most of the architecture. Instead, alternative architecture concepts are conceivable that emphasize other performance metrics (e.g., memory bandwidth) by treating numeric logic as a high-availability component rather than the current high-utilization requirement with a significant reduction in the herculean structures only intended to keep them (ALU/FPU) busy. While some extensions such as SIMD logic arrays move towards this goal, they are still constrained by the vNa paradigm.

A second strategic impediment imposed by the decades-long vNa legacy is the forced logical and physical separation of the principal system components; processor cores, main memory, and communication channels. This is a consequence of the initial enabling technologies available for these capabilities at the dawn of modern computers. Logic and control were provided by vacuum tubes, thanks in part to John Vincent Atanasoff. Data storage for main memory went through multiple technologies within a very few years but distinct from their logic technology. Mercury delay lines, magnetic drums, Williams tubes, punch cards, paper tape, and ultimately magnetic cores (invented at MIT) were all used in turn or in various mixes to represent, store, and deliver binary data. And data communication was just wire (using pulse-mode transfer) without worrying much about bandwidth over moderate distances within a mainframe. Of course, Claude Shannon had addressed that problem in the previous decade with the abstraction of information theory and the bit. Thus, in the incipient vNa era, this separation was natural and required being well served by the von Neumann paradigm. Over the next two decades, refined magnetic cores dominated the memory market while logic remained separate but transformational; from vacuum tubes to transistors (germanium and silicon), to early generation integrated circuits. The challenge of data transfer did come into its own with sensitivity to communication bandwidth and latency. But the dominant structure of differentiated functional purpose and physical separation has remained the same. With the advent of VLSI semiconductor devices: including the microprocessor and DRAM, the need for this disparity and separation of component technology has been largely eliminated; at least between the processor cores and the main memory.

A particular ramification of this segregation of functional components is what is sometimes referred to as the “von Neumann bottleneck” (although this term has various meanings in its usage). Latency, contention, overhead, and limitation of parallelism are all results, at least in part, due to the separation of the memory from the execution logic. Latency is made far worse than physically necessary by distancing main memory components from processing logic. Delays due to bandwidth of communication channels increase contention for memory access by processor cores. Managing data transfers through a separate network channel forces more overhead work, potentially in the critical path.

A third legacy of the vNa is the adherence and implementation of sequential flow control to sequence the operations during program execution. At its conceptual introduction, the vNa was well tuned to the enabling technologies of the era with the cycle times of both the logic and the memory devices roughly comparable. The complexity of the operations was reflected by the complexity of the hardware design and was minimized by use of the sequential program counter (i.e., instruction pointer). Management of the compute cycle including instruction fetch, execute, and write-back was hard enough to achieve with the components at hand. At that time and in to the 1960s this was sufficiently costly to implement that methods were tried to reduce such cost. Bit-sequential architecture like the PDP-8/S and storing of the program counter in the 0’th location of memory like the PDP-5 were designed to substantially reduce cost, at a time when discrete transistors and first generation ICs were relatively expensive in large ensembles such as the construction of computers, even mini-computers.

Critical to performance, both throughput and time to solution (weak and strong scaling), is operational parallelism, which in many forms has been integrated with vNa to perform multiple operations simultaneously. Even in single-processor cores, pipelining, like the execution pipeline and SIMD, pick off bits of the opportunity to exploit parallelism, still within the overall framework of vNa. But at its core (meant both ways) is serial processing to minimize complexity and cost. In later designs, even in the recent decades, the venerable instruction pointer is retained with parallelism built on top of it both in hardware and software; this in lieu of replacing the historical vNa execution model with a more appropriate intrinsically parallel computing paradigm both to reduce overheads and increase scalability. Even with those add-on concurrency mechanisms, memory access ordering is over constrained to retain the semblance of sequential consistency, again, when the freedom of parallelism is required. While parallel execution has been captured to some degree with industrial grade SIMD, CSP, and PRAM, these all are narrow in exposing and exploiting inherent parallelism in its many facets.

The patchwork of clever but costly add-ons to computing over the recent decades is due, to a significant degree, to the continued assumption and incorporation of the foundational requirements of the vNa model, even when it no longer is optimal with contemporary enabling technologies. Examples of these patchwork add-ons are pervasive; they aren’t even considered as a choice. Caches are intended as a user transparent way of matching the speeds of logic to the storage capacities of main memory. But their effectiveness is limited by dependence on temporal and spatial locality and the amount of die area they consume of the processor core. In addition, hardware support for cache coherence is included, taking up more space, time and energy to maintain sequential consistency when relaxed consistency or other memory models are required. To keep arithmetic units highly utilized, even when this is no longer the best objective function, complex mechanisms for speculative execution are incorporated to keep many memory accesses in-flight although most are never used, branch prediction to avoid delays in sequential conditional operations, TLBs for virtual page access (a slightly different issue), high speed buffering for memory access asynchronies, among others.

The opportunity to dramatically reduce die area per operation, overheads per action, latency per access, synchronization delays within a variable asynchronous context, and contention for communication and ALU channels is in front of us through architecture redefinition and new execution models supported by advanced runtime. But this requires replacement of the von Neumann architecture as system designs are aggressively advanced. HPC is at a pivotal singularity with both resistance to and innovation of change of computing architectures in the age of nanoscale.

Dr. Thomas Sterling holds the position of Professor of Intelligent Systems Engineering at the Indiana University (IU) School of Informatics, Computing, and Engineering. Since receiving his Ph.D from MIT in 1984 as a Hertz Fellow Dr. Sterling has engaged in applied research in fields associated with parallel computing system structures, semantics, and operation in industry, government labs, and academia. Dr. Sterling is best known as the “father of Beowulf” for his pioneering research in commodity/Linux cluster computing. He was awarded the Gordon Bell Prize in 1997 with his collaborators for this work.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Research: A Survey of Numerical Methods Utilizing Mixed Precision Arithmetic

August 5, 2020

Within the past years, hardware vendors have started designing low precision special function units in response to the demand of the machine learning community and their demand for high compute power in low precision for Read more…

By Hartwig Anzt and Jack Dongarra

Implement Photonic Tensor Cores for Machine Learning?

August 5, 2020

Researchers from George Washington University have reported an approach for building photonic tensor cores that leverages phase change photonic memory to implement a neural network (NN). Their novel architecture, reporte Read more…

By John Russell

HPE Keeps Cray Brand Promise, Reveals HPE Cray Supercomputing Line

August 4, 2020

The HPC community, ever-affectionate toward Cray and its eponymous founder, can breathe a (virtual) sigh of relief. The Cray brand will live on, encompassing the pinnacle of HPE's HPC portfolio. After announcing its i Read more…

By Tiffany Trader

Machines, Connections, Data, and Especially People: OAC Acting Director Amy Friedlander Charts Office’s Blueprint for Innovation

August 3, 2020

The path to innovation in cyberinfrastructure (CI) will require continued focus on building HPC systems and secure connections between them, in addition to the increasingly important goals of data best practices and work Read more…

By Ken Chiacchia, Pittsburgh Supercomputing Center/XSEDE

Nvidia Said to Be Close on Arm Deal

August 3, 2020

GPU leader Nvidia Corp. is in talks to buy U.K. chip designer Arm from parent company Softbank, according to several reports over the weekend. If consummated, analysts said the acquisition would cement Nvidia’s stat Read more…

By George Leopold

AWS Solution Channel

AWS announces the release of AWS ParallelCluster 2.8.0

AWS ParallelCluster is a fully supported and maintained open source cluster management tool that makes it easy for scientists, researchers, and IT administrators to deploy and manage High Performance Computing (HPC) clusters in the AWS cloud. Read more…

Intel® HPC + AI Pavilion

Supercomputing the Pandemic: Scientific Community Tackles COVID-19 from Multiple Perspectives

Since their inception, supercomputers have taken on the biggest, most complex, and most data-intensive computing challenges—from confirming Einstein’s theories about gravitational waves to predicting the impacts of climate change. Read more…

Summer Reading: Here’s a Quantum Advantage You Can Bet On!

August 3, 2020

While quantum computing researchers today vigorously chase a demonstration of a quantum advantage – an application which when run on a quantum computer provides sufficient advantage to warrant switching from a classica Read more…

By John Russell

HPE Keeps Cray Brand Promise, Reveals HPE Cray Supercomputing Line

August 4, 2020

The HPC community, ever-affectionate toward Cray and its eponymous founder, can breathe a (virtual) sigh of relief. The Cray brand will live on, encompassing th Read more…

By Tiffany Trader

Machines, Connections, Data, and Especially People: OAC Acting Director Amy Friedlander Charts Office’s Blueprint for Innovation

August 3, 2020

The path to innovation in cyberinfrastructure (CI) will require continued focus on building HPC systems and secure connections between them, in addition to the Read more…

By Ken Chiacchia, Pittsburgh Supercomputing Center/XSEDE

Nvidia Said to Be Close on Arm Deal

August 3, 2020

GPU leader Nvidia Corp. is in talks to buy U.K. chip designer Arm from parent company Softbank, according to several reports over the weekend. If consummated Read more…

By George Leopold

Intel’s 7nm Slip Raises Questions About Ponte Vecchio GPU, Aurora Supercomputer

July 30, 2020

During its second-quarter earnings call, Intel announced a one-year delay of its 7nm process technology, which it says it will create an approximate six-month shift for its CPU product timing relative to prior expectations. The primary issue is a defect mode in the 7nm process that resulted in yield degradation... Read more…

By Tiffany Trader

PEARC20 Plenary Introduces Five Upcoming NSF-Funded HPC Systems

July 30, 2020

Five new HPC systems—three National Science Foundation-funded “Capacity” systems and two “Innovative Prototype/Testbed” systems—will be coming onlin Read more…

By Ken Chiacchia, Pittsburgh Supercomputing Center/XSEDE

Nvidia Dominates Latest MLPerf Training Benchmark Results

July 29, 2020

MLPerf.org released its third round of training benchmark (v0.7) results today and Nvidia again dominated, claiming 16 new records. Meanwhile, Google provided e Read more…

By John Russell

$39 Billion Worldwide HPC Market Faces 3.7% COVID-related Drop in 2020

July 29, 2020

Global HPC market revenue reached $39 billion in 2019, growing a healthy 8.2 percent over 2018, according to the latest analysis from Intersect360 Research. A 3 Read more…

By Tiffany Trader

Agenting Change: PEARC20 Keynote Encourages Cultural Change to Make Tech Better, More Diverse

July 29, 2020

The tech world will need to become more diverse if it is to thrive and survive, said Cherri Pancake, director of the Northwest Alliance for Computational Resear Read more…

By Ken Chiacchia, Pittsburgh Supercomputing Center/XSEDE

Supercomputer Modeling Tests How COVID-19 Spreads in Grocery Stores

April 8, 2020

In the COVID-19 era, many people are treating simple activities like getting gas or groceries with caution as they try to heed social distancing mandates and protect their own health. Still, significant uncertainty surrounds the relative risk of different activities, and conflicting information is prevalent. A team of Finnish researchers set out to address some of these uncertainties by... Read more…

By Oliver Peckham

Supercomputer-Powered Research Uncovers Signs of ‘Bradykinin Storm’ That May Explain COVID-19 Symptoms

July 28, 2020

Doctors and medical researchers have struggled to pinpoint – let alone explain – the deluge of symptoms induced by COVID-19 infections in patients, and what Read more…

By Oliver Peckham

Intel’s 7nm Slip Raises Questions About Ponte Vecchio GPU, Aurora Supercomputer

July 30, 2020

During its second-quarter earnings call, Intel announced a one-year delay of its 7nm process technology, which it says it will create an approximate six-month shift for its CPU product timing relative to prior expectations. The primary issue is a defect mode in the 7nm process that resulted in yield degradation... Read more…

By Tiffany Trader

Supercomputer Simulations Reveal the Fate of the Neanderthals

May 25, 2020

For hundreds of thousands of years, neanderthals roamed the planet, eventually (almost 50,000 years ago) giving way to homo sapiens, which quickly became the do Read more…

By Oliver Peckham

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

By Doug Black

Neocortex Will Be First-of-Its-Kind 800,000-Core AI Supercomputer

June 9, 2020

Pittsburgh Supercomputing Center (PSC - a joint research organization of Carnegie Mellon University and the University of Pittsburgh) has won a $5 million award Read more…

By Tiffany Trader

Nvidia Said to Be Close on Arm Deal

August 3, 2020

GPU leader Nvidia Corp. is in talks to buy U.K. chip designer Arm from parent company Softbank, according to several reports over the weekend. If consummated Read more…

By George Leopold

Nvidia’s Ampere A100 GPU: Up to 2.5X the HPC, 20X the AI

May 14, 2020

Nvidia's first Ampere-based graphics card, the A100 GPU, packs a whopping 54 billion transistors on 826mm2 of silicon, making it the world's largest seven-nanom Read more…

By Tiffany Trader

Leading Solution Providers

Contributors

Honeywell’s Big Bet on Trapped Ion Quantum Computing

April 7, 2020

Honeywell doesn’t spring to mind when thinking of quantum computing pioneers, but a decade ago the high-tech conglomerate better known for its control systems waded deliberately into the then calmer quantum computing (QC) waters. Fast forward to March when Honeywell announced plans to introduce an ion trap-based quantum computer whose ‘performance’ would... Read more…

By John Russell

Australian Researchers Break All-Time Internet Speed Record

May 26, 2020

If you’ve been stuck at home for the last few months, you’ve probably become more attuned to the quality (or lack thereof) of your internet connection. Even Read more…

By Oliver Peckham

15 Slides on Programming Aurora and Exascale Systems

May 7, 2020

Sometime in 2021, Aurora, the first planned U.S. exascale system, is scheduled to be fired up at Argonne National Laboratory. Cray (now HPE) and Intel are the k Read more…

By John Russell

‘Billion Molecules Against COVID-19’ Challenge to Launch with Massive Supercomputing Support

April 22, 2020

Around the world, supercomputing centers have spun up and opened their doors for COVID-19 research in what may be the most unified supercomputing effort in hist Read more…

By Oliver Peckham

Joliot-Curie Supercomputer Used to Build First Full, High-Fidelity Aircraft Engine Simulation

July 14, 2020

When industrial designers plan the design of a new element of a vehicle’s propulsion or exterior, they typically use fluid dynamics to optimize airflow and in Read more…

By Oliver Peckham

$100B Plan Submitted for Massive Remake and Expansion of NSF

May 27, 2020

Legislation to reshape, expand - and rename - the National Science Foundation has been submitted in both the U.S. House and Senate. The proposal, which seems to Read more…

By John Russell

John Martinis Reportedly Leaves Google Quantum Effort

April 21, 2020

John Martinis, who led Google’s quantum computing effort since establishing its quantum hardware group in 2014, has left Google after being moved into an advi Read more…

By John Russell

Google Cloud Debuts 16-GPU Ampere A100 Instances

July 7, 2020

On the heels of the Nvidia’s Ampere A100 GPU launch in May, Google Cloud is announcing alpha availability of the A100 “Accelerator Optimized” VM A2 instance family on Google Compute Engine. The instances are powered by the HGX A100 16-GPU platform, which combines two HGX A100 8-GPU baseboards using... Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This