A Declaration of Interdependence through Non von Neumann Architecture

By Thomas Sterling, Indiana University

July 22, 2020

Editor’s note: Where does computing architecture go from here? That’s an ambitious question for sure, perhaps overly ambitious, but tackling ambitious ideas has been the habit of Thomas Sterling, Professor of Intelligent Systems Engineering at the Indiana University (IU) School of Informatics, Computing, and Engineering. In this first of two contributed pieces, Sterling examines the early strengths and later inhibiting consequences of settling on von Neumann architecture (vNa), which for years fueled spectacular growth but now has become a roadblock. The ALU is king in vNa and maximizing its use is the driving principle. Sterling looks at why that thinking no longer holds. In his second article Sterling will examine alternative directions to push past vNa into various Non von Neumann architectures. Enjoy.

The unprecedented success of the von Neumann architecture (vNa) and its many derivatives over the last seven decades has yielded a performance-gain in excess of ten trillion-fold exceeding the progress of any other technology in human history by orders of magnitude. The abstract vNa has become the integral aspect of the HPC corporate mentality that it serves as the standard for general-purpose computing with all other forms of structures relegated to “special purpose,” “domain specific,” “accelerators,” “GPUs,” and others.

In addition to the elegance and simplicity of vNa, it was also of true practical value serving as a template for the organization and semantics of digital electronics hardware to be fabricated not only with the enabling technologies of that era (circa 1950) but also across a succession of technology advances for decades beyond. This suitability to effectively leverage the functionality and capability of available underlying device types is a major factor in the past success of vNa. However, this is not only no longer the case, it is in increasing conflict with ability to optimize the use of contemporary and future semiconductor technologies that must drive a much-needed architecture transformation to extend the efficiency and scalability of future generation HPC systems. This first of two articles describes the poor fit of the original vNa concepts to the current semiconductor enabling technologies at the end of Moore’s law and practical power constraints. The constructive contribution of this is the exposure and identification of intrinsic latent opportunities for dramatic improvements in performance. Through relaxation of limiting properties imposed by the assumption of vNa family of execution models, semantics, and structures, a leap in future performance of HPC may yet be gained. The second article, at the discretion of HPCwire, will suggest aspects of Non von Neumann architectures (NvNa), some already in consideration or even employed, that can exploit these opportunities recognizing that there is not only one answer, nor any one answer that fully addresses all needs and choices.

John von Neumann in the 1940s (Wikimedia Commons)

The most pernicious of the legacy factors implicit in the classical von Neumann architecture is its fundamental objective function; that is its choice of resource considered as precious and for which the resulting designs are optimized. Sophisticated designs attempt to devise “balanced architectures” mixing investment of resources to a multi-dimensional “best” including normalizing factors such as cost, area, or energy consumption. But at the risk of over-simplifying, historically the precious resource of vNa derivatives is the rate of performing numeric operations, often more specifically the floating-point throughput. This is certainly reflected by the HPC community adoption of the HPL (High-Performance Linpack) benchmark which measures the floating-point performance of a specific dense-matrix algorithm dominated by double precision floating-point addition and multiplication operations, Rmax. John von Neumann and his University of Pennsylvania colleagues J. Presper Eckert and John Mauchly recognized, chiefly through their experiences in the development of ENIAC by the US Army, that the arithmetic logic unit (ALU) was among the most complicated and component-intensive elements of a digital electronic calculating engine possibly making it the most expensive and motivating treating it as the critical-path element of the vNa. Although memory might have also been considered as the pacing item (and was in many ways), the focus reasonably remained on logic.

Through the technology generations of 1) vacuum tubes, 2) germanium transistors, 3) silicon transistors, 4) SSI and 5) MSI, the large ALUs and FPUs dominated the architecture design based on the traditional vNa concepts even as innovative structures such as pipelining for execution and floating point, locality based caches, speculative actions such as branch prediction, introduction of virtual memory with TLBs, register banks, Tomasulo-based reservation stations, and other creative optimizations advanced the state-of-the-art dramatically from its incipient implementations such as Cambridge EDSAC, MIT Whirlwind, and the ERA 1101. But at all times, arithmetic performance was supported by the rest of the processor architecture. By the early years of the 21st century, the balance of die area was shifting as the feature-size improved exponentially. The actual arithmetic units became an ever-decreasing proportion of the overall processor core die area. Yet, in accordance with tradition, the majority of the die was dedicated to support the throughput of the minority of the die allocated to the FPU. This upside-down optimization continues to stress FPU utilization at the cost (in area) of most of the architecture. Instead, alternative architecture concepts are conceivable that emphasize other performance metrics (e.g., memory bandwidth) by treating numeric logic as a high-availability component rather than the current high-utilization requirement with a significant reduction in the herculean structures only intended to keep them (ALU/FPU) busy. While some extensions such as SIMD logic arrays move towards this goal, they are still constrained by the vNa paradigm.

A second strategic impediment imposed by the decades-long vNa legacy is the forced logical and physical separation of the principal system components; processor cores, main memory, and communication channels. This is a consequence of the initial enabling technologies available for these capabilities at the dawn of modern computers. Logic and control were provided by vacuum tubes, thanks in part to John Vincent Atanasoff. Data storage for main memory went through multiple technologies within a very few years but distinct from their logic technology. Mercury delay lines, magnetic drums, Williams tubes, punch cards, paper tape, and ultimately magnetic cores (invented at MIT) were all used in turn or in various mixes to represent, store, and deliver binary data. And data communication was just wire (using pulse-mode transfer) without worrying much about bandwidth over moderate distances within a mainframe. Of course, Claude Shannon had addressed that problem in the previous decade with the abstraction of information theory and the bit. Thus, in the incipient vNa era, this separation was natural and required being well served by the von Neumann paradigm. Over the next two decades, refined magnetic cores dominated the memory market while logic remained separate but transformational; from vacuum tubes to transistors (germanium and silicon), to early generation integrated circuits. The challenge of data transfer did come into its own with sensitivity to communication bandwidth and latency. But the dominant structure of differentiated functional purpose and physical separation has remained the same. With the advent of VLSI semiconductor devices: including the microprocessor and DRAM, the need for this disparity and separation of component technology has been largely eliminated; at least between the processor cores and the main memory.

A particular ramification of this segregation of functional components is what is sometimes referred to as the “von Neumann bottleneck” (although this term has various meanings in its usage). Latency, contention, overhead, and limitation of parallelism are all results, at least in part, due to the separation of the memory from the execution logic. Latency is made far worse than physically necessary by distancing main memory components from processing logic. Delays due to bandwidth of communication channels increase contention for memory access by processor cores. Managing data transfers through a separate network channel forces more overhead work, potentially in the critical path.

A third legacy of the vNa is the adherence and implementation of sequential flow control to sequence the operations during program execution. At its conceptual introduction, the vNa was well tuned to the enabling technologies of the era with the cycle times of both the logic and the memory devices roughly comparable. The complexity of the operations was reflected by the complexity of the hardware design and was minimized by use of the sequential program counter (i.e., instruction pointer). Management of the compute cycle including instruction fetch, execute, and write-back was hard enough to achieve with the components at hand. At that time and in to the 1960s this was sufficiently costly to implement that methods were tried to reduce such cost. Bit-sequential architecture like the PDP-8/S and storing of the program counter in the 0’th location of memory like the PDP-5 were designed to substantially reduce cost, at a time when discrete transistors and first generation ICs were relatively expensive in large ensembles such as the construction of computers, even mini-computers.

Critical to performance, both throughput and time to solution (weak and strong scaling), is operational parallelism, which in many forms has been integrated with vNa to perform multiple operations simultaneously. Even in single-processor cores, pipelining, like the execution pipeline and SIMD, pick off bits of the opportunity to exploit parallelism, still within the overall framework of vNa. But at its core (meant both ways) is serial processing to minimize complexity and cost. In later designs, even in the recent decades, the venerable instruction pointer is retained with parallelism built on top of it both in hardware and software; this in lieu of replacing the historical vNa execution model with a more appropriate intrinsically parallel computing paradigm both to reduce overheads and increase scalability. Even with those add-on concurrency mechanisms, memory access ordering is over constrained to retain the semblance of sequential consistency, again, when the freedom of parallelism is required. While parallel execution has been captured to some degree with industrial grade SIMD, CSP, and PRAM, these all are narrow in exposing and exploiting inherent parallelism in its many facets.

The patchwork of clever but costly add-ons to computing over the recent decades is due, to a significant degree, to the continued assumption and incorporation of the foundational requirements of the vNa model, even when it no longer is optimal with contemporary enabling technologies. Examples of these patchwork add-ons are pervasive; they aren’t even considered as a choice. Caches are intended as a user transparent way of matching the speeds of logic to the storage capacities of main memory. But their effectiveness is limited by dependence on temporal and spatial locality and the amount of die area they consume of the processor core. In addition, hardware support for cache coherence is included, taking up more space, time and energy to maintain sequential consistency when relaxed consistency or other memory models are required. To keep arithmetic units highly utilized, even when this is no longer the best objective function, complex mechanisms for speculative execution are incorporated to keep many memory accesses in-flight although most are never used, branch prediction to avoid delays in sequential conditional operations, TLBs for virtual page access (a slightly different issue), high speed buffering for memory access asynchronies, among others.

The opportunity to dramatically reduce die area per operation, overheads per action, latency per access, synchronization delays within a variable asynchronous context, and contention for communication and ALU channels is in front of us through architecture redefinition and new execution models supported by advanced runtime. But this requires replacement of the von Neumann architecture as system designs are aggressively advanced. HPC is at a pivotal singularity with both resistance to and innovation of change of computing architectures in the age of nanoscale.

Dr. Thomas Sterling holds the position of Professor of Intelligent Systems Engineering at the Indiana University (IU) School of Informatics, Computing, and Engineering. Since receiving his Ph.D from MIT in 1984 as a Hertz Fellow Dr. Sterling has engaged in applied research in fields associated with parallel computing system structures, semantics, and operation in industry, government labs, and academia. Dr. Sterling is best known as the “father of Beowulf” for his pioneering research in commodity/Linux cluster computing. He was awarded the Gordon Bell Prize in 1997 with his collaborators for this work.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Intel Reorgs HPC Group, Creates Two ‘Super Compute’ Groups

October 15, 2021

Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing... Read more…

Royalty-free stock illustration ID: 1938746143

MosaicML, Led by Naveen Rao, Comes Out of Stealth Aiming to Ease Model Training

October 15, 2021

With more and more enterprises turning to AI for a myriad of tasks, companies quickly find out that training AI models is expensive, difficult and time-consuming. Finding a new approach to deal with those cascading challenges is the aim of a new startup, MosaicML, that just came out of stealth... Read more…

NSF Awards $11M to SDSC, MIT and Univ. of Oregon to Secure the Internet

October 14, 2021

From a security standpoint, the internet is a problem. The infrastructure developed decades ago has cracked, leaked and been patched up innumerable times, leaving vulnerabilities that are difficult to address due to cost Read more…

SC21 Announces Science and Beyond Plenary: the Intersection of Ethics and HPC

October 13, 2021

The Intersection of Ethics and HPC will be the guiding topic of SC21's Science & Beyond plenary, inspired by the event tagline of the same name. The evening event will be moderated by Daniel Reed with panelists Crist Read more…

Quantum Workforce – NSTC Report Highlights Need for International Talent

October 13, 2021

Attracting and training the needed quantum workforce to fuel the ongoing quantum information sciences (QIS) revolution is a hot topic these days. Last week, the U.S. National Science and Technology Council issued a report – The Role of International Talent in Quantum Information Science... Read more…

AWS Solution Channel

Cost optimizing Ansys LS-Dyna on AWS

Organizations migrate their high performance computing (HPC) workloads from on-premises infrastructure to Amazon Web Services (AWS) for advantages such as high availability, elastic capacity, latest processors, storage, and networking technologies; Read more…

Eni Returns to HPE for ‘HPC4’ Refresh via GreenLake

October 13, 2021

Italian energy company Eni is upgrading its HPC4 system with new gear from HPE that will be installed in Eni’s Green Data Center in Ferrera Erbognone (a province in Pavia, Italy), and delivered “as-a-service” via H Read more…

Intel Reorgs HPC Group, Creates Two ‘Super Compute’ Groups

October 15, 2021

Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing... Read more…

Royalty-free stock illustration ID: 1938746143

MosaicML, Led by Naveen Rao, Comes Out of Stealth Aiming to Ease Model Training

October 15, 2021

With more and more enterprises turning to AI for a myriad of tasks, companies quickly find out that training AI models is expensive, difficult and time-consuming. Finding a new approach to deal with those cascading challenges is the aim of a new startup, MosaicML, that just came out of stealth... Read more…

Quantum Workforce – NSTC Report Highlights Need for International Talent

October 13, 2021

Attracting and training the needed quantum workforce to fuel the ongoing quantum information sciences (QIS) revolution is a hot topic these days. Last week, the U.S. National Science and Technology Council issued a report – The Role of International Talent in Quantum Information Science... Read more…

Eni Returns to HPE for ‘HPC4’ Refresh via GreenLake

October 13, 2021

Italian energy company Eni is upgrading its HPC4 system with new gear from HPE that will be installed in Eni’s Green Data Center in Ferrera Erbognone (a provi Read more…

The Blueprint for the National Strategic Computing Reserve

October 12, 2021

Over the last year, the HPC community has been buzzing with the possibility of a National Strategic Computing Reserve (NSCR). An in-utero brainchild of the COVID-19 High-Performance Computing Consortium, an NSCR would serve as a Merchant Marine for urgent computing... Read more…

UCLA Researchers Report Largest Chiplet Design and Early Prototyping

October 12, 2021

What’s the best path forward for large-scale chip/system integration? Good question. Cerebras has set a high bar with its wafer scale engine 2 (WSE-2); it has 2.6 trillion transistors, including 850,000 cores, and was fabricated using TSMC’s 7nm process on a roughly 8” x 8” silicon footprint. Read more…

What’s Next for EuroHPC: an Interview with EuroHPC Exec. Dir. Anders Dam Jensen

October 7, 2021

One year after taking the post as executive director of the EuroHPC JU, Anders Dam Jensen reviews the project's accomplishments and details what's ahead as EuroHPC's operating period has now been extended out to the year 2027. Read more…

University of Bath Unveils Janus, an Azure-Based Cloud HPC Environment

October 6, 2021

The University of Bath is upgrading its HPC infrastructure, which it says “supports a growing and wide range of research activities across the University.” Read more…

Ahead of ‘Dojo,’ Tesla Reveals Its Massive Precursor Supercomputer

June 22, 2021

In spring 2019, Tesla made cryptic reference to a project called Dojo, a “super-powerful training computer” for video data processing. Then, in summer 2020, Tesla CEO Elon Musk tweeted: “Tesla is developing a [neural network] training computer... Read more…

Enter Dojo: Tesla Reveals Design for Modular Supercomputer & D1 Chip

August 20, 2021

Two months ago, Tesla revealed a massive GPU cluster that it said was “roughly the number five supercomputer in the world,” and which was just a precursor to Tesla’s real supercomputing moonshot: the long-rumored, little-detailed Dojo system. Read more…

Esperanto, Silicon in Hand, Champions the Efficiency of Its 1,092-Core RISC-V Chip

August 27, 2021

Esperanto Technologies made waves last December when it announced ET-SoC-1, a new RISC-V-based chip aimed at machine learning that packed nearly 1,100 cores onto a package small enough to fit six times over on a single PCIe card. Now, Esperanto is back, silicon in-hand and taking aim... Read more…

CentOS Replacement Rocky Linux Is Now in GA and Under Independent Control

June 21, 2021

The Rocky Enterprise Software Foundation (RESF) is announcing the general availability of Rocky Linux, release 8.4, designed as a drop-in replacement for the soon-to-be discontinued CentOS. The GA release is launching six-and-a-half months... Read more…

US Closes in on Exascale: Frontier Installation Is Underway

September 29, 2021

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, held by Zoom this week (Sept. 29-30), it was revealed that the Frontier supercomputer is currently being installed at Oak Ridge National Laboratory in Oak Ridge, Tenn. The staff at the Oak Ridge Leadership... Read more…

Intel Completes LLVM Adoption; Will End Updates to Classic C/C++ Compilers in Future

August 10, 2021

Intel reported in a blog this week that its adoption of the open source LLVM architecture for Intel’s C/C++ compiler is complete. The transition is part of In Read more…

Hot Chips: Here Come the DPUs and IPUs from Arm, Nvidia and Intel

August 25, 2021

The emergence of data processing units (DPU) and infrastructure processing units (IPU) as potentially important pieces in cloud and datacenter architectures was Read more…

AMD-Xilinx Deal Gains UK, EU Approvals — China’s Decision Still Pending

July 1, 2021

AMD’s planned acquisition of FPGA maker Xilinx is now in the hands of Chinese regulators after needed antitrust approvals for the $35 billion deal were receiv Read more…

Leading Solution Providers

Contributors

HPE Wins $2B GreenLake HPC-as-a-Service Deal with NSA

September 1, 2021

In the heated, oft-contentious, government IT space, HPE has won a massive $2 billion contract to provide HPC and AI services to the United States’ National Security Agency (NSA). Following on the heels of the now-canceled $10 billion JEDI contract (reissued as JWCC) and a $10 billion... Read more…

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

Quantum Roundup: IBM, Rigetti, Phasecraft, Oxford QC, China, and More

July 13, 2021

IBM yesterday announced a proof for a quantum ML algorithm. A week ago, it unveiled a new topology for its quantum processors. Last Friday, the Technical Univer Read more…

The Latest MLPerf Inference Results: Nvidia GPUs Hold Sway but Here Come CPUs and Intel

September 22, 2021

The latest round of MLPerf inference benchmark (v 1.1) results was released today and Nvidia again dominated, sweeping the top spots in the closed (apples-to-ap Read more…

Frontier to Meet 20MW Exascale Power Target Set by DARPA in 2008

July 14, 2021

After more than a decade of planning, the United States’ first exascale computer, Frontier, is set to arrive at Oak Ridge National Laboratory (ORNL) later this year. Crossing this “1,000x” horizon required overcoming four major challenges: power demand, reliability, extreme parallelism and data movement. Read more…

Intel Unveils New Node Names; Sapphire Rapids Is Now an ‘Intel 7’ CPU

July 27, 2021

What's a preeminent chip company to do when its process node technology lags the competition by (roughly) one generation, but outmoded naming conventions make i Read more…

Intel Launches 10nm ‘Ice Lake’ Datacenter CPU with Up to 40 Cores

April 6, 2021

The wait is over. Today Intel officially launched its 10nm datacenter CPU, the third-generation Intel Xeon Scalable processor, codenamed Ice Lake. With up to 40 Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire