A Declaration of Interdependence through Non von Neumann Architecture

By Thomas Sterling, Indiana University

July 22, 2020

Editor’s note: Where does computing architecture go from here? That’s an ambitious question for sure, perhaps overly ambitious, but tackling ambitious ideas has been the habit of Thomas Sterling, Professor of Intelligent Systems Engineering at the Indiana University (IU) School of Informatics, Computing, and Engineering. In this first of two contributed pieces, Sterling examines the early strengths and later inhibiting consequences of settling on von Neumann architecture (vNa), which for years fueled spectacular growth but now has become a roadblock. The ALU is king in vNa and maximizing its use is the driving principle. Sterling looks at why that thinking no longer holds. In his second article Sterling will examine alternative directions to push past vNa into various Non von Neumann architectures. Enjoy.

The unprecedented success of the von Neumann architecture (vNa) and its many derivatives over the last seven decades has yielded a performance-gain in excess of ten trillion-fold exceeding the progress of any other technology in human history by orders of magnitude. The abstract vNa has become the integral aspect of the HPC corporate mentality that it serves as the standard for general-purpose computing with all other forms of structures relegated to “special purpose,” “domain specific,” “accelerators,” “GPUs,” and others.

In addition to the elegance and simplicity of vNa, it was also of true practical value serving as a template for the organization and semantics of digital electronics hardware to be fabricated not only with the enabling technologies of that era (circa 1950) but also across a succession of technology advances for decades beyond. This suitability to effectively leverage the functionality and capability of available underlying device types is a major factor in the past success of vNa. However, this is not only no longer the case, it is in increasing conflict with ability to optimize the use of contemporary and future semiconductor technologies that must drive a much-needed architecture transformation to extend the efficiency and scalability of future generation HPC systems. This first of two articles describes the poor fit of the original vNa concepts to the current semiconductor enabling technologies at the end of Moore’s law and practical power constraints. The constructive contribution of this is the exposure and identification of intrinsic latent opportunities for dramatic improvements in performance. Through relaxation of limiting properties imposed by the assumption of vNa family of execution models, semantics, and structures, a leap in future performance of HPC may yet be gained. The second article, at the discretion of HPCwire, will suggest aspects of Non von Neumann architectures (NvNa), some already in consideration or even employed, that can exploit these opportunities recognizing that there is not only one answer, nor any one answer that fully addresses all needs and choices.

John von Neumann in the 1940s (Wikimedia Commons)

The most pernicious of the legacy factors implicit in the classical von Neumann architecture is its fundamental objective function; that is its choice of resource considered as precious and for which the resulting designs are optimized. Sophisticated designs attempt to devise “balanced architectures” mixing investment of resources to a multi-dimensional “best” including normalizing factors such as cost, area, or energy consumption. But at the risk of over-simplifying, historically the precious resource of vNa derivatives is the rate of performing numeric operations, often more specifically the floating-point throughput. This is certainly reflected by the HPC community adoption of the HPL (High-Performance Linpack) benchmark which measures the floating-point performance of a specific dense-matrix algorithm dominated by double precision floating-point addition and multiplication operations, Rmax. John von Neumann and his University of Pennsylvania colleagues J. Presper Eckert and John Mauchly recognized, chiefly through their experiences in the development of ENIAC by the US Army, that the arithmetic logic unit (ALU) was among the most complicated and component-intensive elements of a digital electronic calculating engine possibly making it the most expensive and motivating treating it as the critical-path element of the vNa. Although memory might have also been considered as the pacing item (and was in many ways), the focus reasonably remained on logic.

Through the technology generations of 1) vacuum tubes, 2) germanium transistors, 3) silicon transistors, 4) SSI and 5) MSI, the large ALUs and FPUs dominated the architecture design based on the traditional vNa concepts even as innovative structures such as pipelining for execution and floating point, locality based caches, speculative actions such as branch prediction, introduction of virtual memory with TLBs, register banks, Tomasulo-based reservation stations, and other creative optimizations advanced the state-of-the-art dramatically from its incipient implementations such as Cambridge EDSAC, MIT Whirlwind, and the ERA 1101. But at all times, arithmetic performance was supported by the rest of the processor architecture. By the early years of the 21st century, the balance of die area was shifting as the feature-size improved exponentially. The actual arithmetic units became an ever-decreasing proportion of the overall processor core die area. Yet, in accordance with tradition, the majority of the die was dedicated to support the throughput of the minority of the die allocated to the FPU. This upside-down optimization continues to stress FPU utilization at the cost (in area) of most of the architecture. Instead, alternative architecture concepts are conceivable that emphasize other performance metrics (e.g., memory bandwidth) by treating numeric logic as a high-availability component rather than the current high-utilization requirement with a significant reduction in the herculean structures only intended to keep them (ALU/FPU) busy. While some extensions such as SIMD logic arrays move towards this goal, they are still constrained by the vNa paradigm.

A second strategic impediment imposed by the decades-long vNa legacy is the forced logical and physical separation of the principal system components; processor cores, main memory, and communication channels. This is a consequence of the initial enabling technologies available for these capabilities at the dawn of modern computers. Logic and control were provided by vacuum tubes, thanks in part to John Vincent Atanasoff. Data storage for main memory went through multiple technologies within a very few years but distinct from their logic technology. Mercury delay lines, magnetic drums, Williams tubes, punch cards, paper tape, and ultimately magnetic cores (invented at MIT) were all used in turn or in various mixes to represent, store, and deliver binary data. And data communication was just wire (using pulse-mode transfer) without worrying much about bandwidth over moderate distances within a mainframe. Of course, Claude Shannon had addressed that problem in the previous decade with the abstraction of information theory and the bit. Thus, in the incipient vNa era, this separation was natural and required being well served by the von Neumann paradigm. Over the next two decades, refined magnetic cores dominated the memory market while logic remained separate but transformational; from vacuum tubes to transistors (germanium and silicon), to early generation integrated circuits. The challenge of data transfer did come into its own with sensitivity to communication bandwidth and latency. But the dominant structure of differentiated functional purpose and physical separation has remained the same. With the advent of VLSI semiconductor devices: including the microprocessor and DRAM, the need for this disparity and separation of component technology has been largely eliminated; at least between the processor cores and the main memory.

A particular ramification of this segregation of functional components is what is sometimes referred to as the “von Neumann bottleneck” (although this term has various meanings in its usage). Latency, contention, overhead, and limitation of parallelism are all results, at least in part, due to the separation of the memory from the execution logic. Latency is made far worse than physically necessary by distancing main memory components from processing logic. Delays due to bandwidth of communication channels increase contention for memory access by processor cores. Managing data transfers through a separate network channel forces more overhead work, potentially in the critical path.

A third legacy of the vNa is the adherence and implementation of sequential flow control to sequence the operations during program execution. At its conceptual introduction, the vNa was well tuned to the enabling technologies of the era with the cycle times of both the logic and the memory devices roughly comparable. The complexity of the operations was reflected by the complexity of the hardware design and was minimized by use of the sequential program counter (i.e., instruction pointer). Management of the compute cycle including instruction fetch, execute, and write-back was hard enough to achieve with the components at hand. At that time and in to the 1960s this was sufficiently costly to implement that methods were tried to reduce such cost. Bit-sequential architecture like the PDP-8/S and storing of the program counter in the 0’th location of memory like the PDP-5 were designed to substantially reduce cost, at a time when discrete transistors and first generation ICs were relatively expensive in large ensembles such as the construction of computers, even mini-computers.

Critical to performance, both throughput and time to solution (weak and strong scaling), is operational parallelism, which in many forms has been integrated with vNa to perform multiple operations simultaneously. Even in single-processor cores, pipelining, like the execution pipeline and SIMD, pick off bits of the opportunity to exploit parallelism, still within the overall framework of vNa. But at its core (meant both ways) is serial processing to minimize complexity and cost. In later designs, even in the recent decades, the venerable instruction pointer is retained with parallelism built on top of it both in hardware and software; this in lieu of replacing the historical vNa execution model with a more appropriate intrinsically parallel computing paradigm both to reduce overheads and increase scalability. Even with those add-on concurrency mechanisms, memory access ordering is over constrained to retain the semblance of sequential consistency, again, when the freedom of parallelism is required. While parallel execution has been captured to some degree with industrial grade SIMD, CSP, and PRAM, these all are narrow in exposing and exploiting inherent parallelism in its many facets.

The patchwork of clever but costly add-ons to computing over the recent decades is due, to a significant degree, to the continued assumption and incorporation of the foundational requirements of the vNa model, even when it no longer is optimal with contemporary enabling technologies. Examples of these patchwork add-ons are pervasive; they aren’t even considered as a choice. Caches are intended as a user transparent way of matching the speeds of logic to the storage capacities of main memory. But their effectiveness is limited by dependence on temporal and spatial locality and the amount of die area they consume of the processor core. In addition, hardware support for cache coherence is included, taking up more space, time and energy to maintain sequential consistency when relaxed consistency or other memory models are required. To keep arithmetic units highly utilized, even when this is no longer the best objective function, complex mechanisms for speculative execution are incorporated to keep many memory accesses in-flight although most are never used, branch prediction to avoid delays in sequential conditional operations, TLBs for virtual page access (a slightly different issue), high speed buffering for memory access asynchronies, among others.

The opportunity to dramatically reduce die area per operation, overheads per action, latency per access, synchronization delays within a variable asynchronous context, and contention for communication and ALU channels is in front of us through architecture redefinition and new execution models supported by advanced runtime. But this requires replacement of the von Neumann architecture as system designs are aggressively advanced. HPC is at a pivotal singularity with both resistance to and innovation of change of computing architectures in the age of nanoscale.

Dr. Thomas Sterling holds the position of Professor of Intelligent Systems Engineering at the Indiana University (IU) School of Informatics, Computing, and Engineering. Since receiving his Ph.D from MIT in 1984 as a Hertz Fellow Dr. Sterling has engaged in applied research in fields associated with parallel computing system structures, semantics, and operation in industry, government labs, and academia. Dr. Sterling is best known as the “father of Beowulf” for his pioneering research in commodity/Linux cluster computing. He was awarded the Gordon Bell Prize in 1997 with his collaborators for this work.

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