Arm Targets HPC with New Neoverse Platforms

By Tiffany Trader

September 22, 2020

UK-based semiconductor design company Arm today teased details of its Neoverse roadmap, introducing V1 (codenamed Zeus) and N2 (codenamed Perseus), Arm’s second generation N-series platform. The chip IP vendor said the new platforms will deliver 50 percent and 40 percent more single-threaded performance, respectively, over Neoverse N1.

The big news for HPC watchers is Neoverse V1’s support for Scalable Vector Extensions (SVE) — implemented as two vectors of 256 bit width — enabling execution of SIMD integer, bfloat16, or floating-point instructions on wider vector units. SVE is architected to be agnostic to the width of the unit, so that applications compiled for SVE on one platform will run on any valid SVE implementation, which can use 128 bit to 2,048 bit widths (in increments of 128 bit).

“With SVE, we are ensuring portability and longevity of the software code, along with efficient execution,” said Chris Bergey, senior vice president and general manager of Arm’s infrastructure line of business.

Projected performance gains. Wider vectors offer more application performance. Source: Arm

The new SVE features for the V1 Neoverse core draw on Arm’s experience working with Fujitsu on the A64FX platform, the SVE-enabled processor that is at the heart of Fugaku, the world’s top-ranked and first #1 Arm-based supercomputer.

A number of Arm partners are developing Neoverse V1-based solutions aimed at data analytics and high-performance computing workloads, noted Arm’s HPC business lead Brent Gorda. One of these is SiPearl, which selected the Zeus core to power its first-generation server processor that underpins Europe’s exascale plans.

Beyond supercomputing, Gorda cites applications for SVE in media processing, encryption/decryption, network processing, as well as edge environments.

In a pre-briefing held for media last week, Arm presented early emulation results for V1 that show speed up at the implementation level over N1 (see bar graphs above).

Silicon partners will have full control over SVE voltage and frequency transitions, said Bergey. This enables them to run at full frequency while executing SVE code, as Fujitsu’s A64FX CPU is able to do.

Bergey said Arm continues to advance its interconnect roadmap with investments in both CCIX and CXL.

CCIX is used for bidirectional coherent communications, and there’s a lot of flexibility in how it’s used, said Bergey.

While the classical case is multi-socket computing, there is an emerging use case for chiplets. “You’ve heard the benefits: die size goes down, yields goes up, costs go down, and it lets you continue to increase core count and performance,” Bergey said.

Arm is also exploring tightly coupled heterogeneous compute. “With the slowdown of Moore’s law scaling, there is interest in chip-to-chip coupling of ARM CPU complexes with a variety of accelerators and memory,” said Bergey.

Comparison of N-series, V-series and E-series (Source: Arm)

The company likewise has plans for CXL, which provides memory-coherent attachment. Bergey highlights use cases, “the most anticipated [being] memory pooling and expansion.”

It enables “sharing a large pool of memory across a set of connected nodes or it could mean just attaching a large amount of emerging memory to a single node,” he said, highlighting the benefits for machine learning training and inferencing.

While V1 stresses optimal performance for the most demanding workloads, N2 addresses scale-out performance. “It won’t quite have the performance per thread of V1, but it will support more cores in a constant TDP,” said Bergey.

He added that while there is no hard limit to the number of cores per CPU, customers have a TDP that they want to optimize around, which ties to core count targets.

“We’re optimizing around performance for power and performance per area. And that allows you to pack in more cores per TDP. Whether that’s a 250 watt cloud SOC, or a 20 watt 5G base station SOC,” he said.

Arm expects its V1 IP to be implemented on both 7nm and 5nm process nodes with different customers leveraging one of those two nodes depending on their timeframes.

Bergey notes that the performance gains they are projecting for V1 and N2 are IPC-based and not nodal related.

Traction for Arm server chips continues to mount. AWS debuted its N1-based Graviton2 processor last year. Ampere will be sampling its 128-core N1 processors (Altra Max) at the end of this year. Fugaku leveraged a custom Arm-platform (A64FX, developed by Fujitsu and Riken) to set multiple benchmarking records and assist in the fight against COVID-19. Marvell had some success with its Arm implementation ThunderX (claiming the first petascale Arm system in 2018 and racking up several other big design wins), but recently announced a pivot to semi-custom.

The building momentum has notably drawn the attention of chip-cum-datacenter company Nvidia. Having already deepened its support for Arm platforms, Nvidia decided to pursue the company itself. Pending regulatory approval, Nvidia will be acquiring the IP chip arm of parent company Softbank for $40 billion.

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