IBM Research Debuts 2nm Test Chip with 50 Billion Transistors

By Tiffany Trader

May 6, 2021

IBM Research today announced the successful prototyping of the world’s first 2 nanometer chip, fabricated with silicon nanosheet technology on a standard 300mm bulk wafer. With ~50 billion transistors, the chip will enable major leaps in performance and energy efficiency for the next decade, according to IBM. The company’s research arm is projecting 45 percent higher performance or 75 percent lower energy use for its 2m node compared with today’s leading 7nm chips. (Similar performance gains were cited for IBM’s 5nm node, comprising ~30 billion transistors, announced in 2017.)

The target date for 2nm foundry technology to go into production is late 2024, said Mukesh Khare, vice president at IBM Research, in a pre-briefing held earlier this week. He emphasized the importance of having a partner ecosystem that leverages the platform.

Key technology enablers highlighted by IBM Research are:

•  Bottom dielectric isolation – providing the reduction in leakage current that is needed to scale gate length to 12nm.
•  A second generation inner spacer dry process for precise gate control.
•  Extreme ultraviolet (EUV) lithography enabled in the front-end to produce variable nanosheet widths from 15nm to 70nm.
•  A multi-threshold-voltage (Multi-Vt) scheme – enabling threshold voltage control for applications that span from low-power mobile to HPC server chips.

IBM Research has been using EUV since its 7nm node, announced in 2015, but has now enabled EUV patterning at the front-end to create structures for the nanosheet and the gate.

“All the critical layers for the 2nm technology will use single exposure EUV, and that will have significant value and benefit, both in terms of cycle time reduction and defect reduction,” said Khare.

Khare said all these nanosheet enhancements are essential to the 2nm node technology, and he stated that these innovations are what differentiate IBM’s 2nm node from competing technologies, for example TSMC’s 3nm process.

As shown on the graphic below, the node’s transistor has three layers of nanosheet, and each sheet has a width of ~40nm and a height of ~5nm. The pitch is ~44nm, and gate length ~12nm.

Courtesy IBM Research

The 2nm node number does not refer to a specific physical feature on the die. While in past decades, a semiconductor node name would relate to a given feature of the chip, this relationship has dissolved in the era of single-digit process nodes.

Khare described the current naming convention as “a metric that’s a combination of many parameters, including power, performance and density, to enable appropriate value and function that you can put on the chip every two-to-two-and-a-half years.”

Partner focused

IBM highlighted its partner ecosystem, which includes newly added R&D partner Intel, as well as Samsung (which is manufacturing IBM’s upcoming 7nm Power10 chips).

“We expect all our partners to benefit from this [2nm technology] innovation,” said Khare. “We’re very proud of our partnership with Intel and Samsung; that said, Samsung is our manufacturing partner and we’re very proud to have them manufacture our 7nm products.”

IBM has been shifting to a collaborative IP model, where it commercializes its research for partner use rather than (or in addition to) prioritizing its use for IBM’s own products. Arvind Krishna, who ran IBM Research when the 5nm and 7nm nodes were announced (in 2015 and 2017 respectively), is now the company’s CEO.

“The IBM innovation reflected in this new 2nm chip is essential to the entire semiconductor and IT industry,” said Darío Gil, senior vice president and director of IBM Research in a statement. “It is the product of IBM’s approach of taking on hard tech challenges and a demonstration of how breakthroughs can result from sustained investments and a collaborative R&D ecosystem approach.”

Khare echoed similar sentiments. “We’re very proud of being able to build an innovation platform for semiconductor,” he said, “and we’re very proud to be able to bring these world leaders in semiconductor manufacturing, equipment, EDA, materials, all of these companies, to this platform.”

Asked what’s next after 2nm and whether semiconductor miniaturization has hit a wall, Khare gave a nod to future progress, but provided no details. “With all the partners we have in Albany with New York State and NY CREATES, and the amount talent and energy we have, I don’t think there’s a wall that we can’t break through,” he said. “There are more breakthroughs in the pipeline and we will be sharing more as the technology matures.”

The 2nm prototype technology is being developed, manufactured and tested at the IBM Research facility in Albany, NY, which maintains 100,000 square foot of clean room space with 24/7 operation. Since selling its chip manufacturing business to GlobalFoundries in 2015, IBM relies on partners to manufacture production parts for its Power and z platforms.

IBM’s 7nm process technology, manufactured by Samsung, is scheduled to debut in Power10 later this year, six years after the test chip was announced.

IBM Research’s Albany facility, with SUNY Poly. Courtesy of IBM Research.
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