AMD Introduces 3D Chiplets, Demos Vertical Cache on Zen 3 CPUs

By Tiffany Trader

June 2, 2021

At Computex 2021, held virtually this week, AMD showcased a new 3D chiplet architecture that will be used for future high-performance computing products set to debut later this year. AMD said it’s been working closely with semiconductor partner TSMC over the last few years to combine chiplet packaging with die stacking to develop the new technology.

Lisa Su holds up prototype showing new 3D V-Cache technology during Computex 2021 keynote (Source: AMD/YouTube)

The first application of the 3D chiplet is 3D vertical cache (3D V-Cache). To demonstrate the technology, AMD created a prototype by bonding a 3D vertical cache onto an AMD Ryzen 5000 series processor. AMD’s hybrid bond approach with through-silicon vias (TSVs) provides over 200 times the interconnect density of 2D chiplets and more than 15 times the density compared to existing vertical stacking solutions, according to the company. “This enables a much more efficient and denser integration of our IP,” said AMD CEO Lisa Su.

In a comparison demo against AMD’s fastest gaming CPU, the Ryzen 9 5900X, the prototype Ryzen 5900X with 3D V-Cache attached delivered a 12 percent higher frame rate for Xbox Game Studios’ game Gears 5. In benchmarking on five other games, performance increased an average of 15 percent using the 3D V-Cache technology.

The die-to-die interface uses a direct copper-to-copper bond with no solder bumps, said Su. “This approach improves the thermals, the transistor density and interconnect pitch, and it’s only one-third the energy per signal of micro-bump 3D approaches,” Su said. “All of these things make this truly the most advanced and flexible active-on-active silicon stacking technology in the world.”

For the Ryzen 5000 series prototype (show below), AMD stacked a 64MB 7nm SRAM directly on top of each core complex, tripling the L3 cache available to the Zen 3 cores. The through-silicon vias pass signals and power between the stacked chips, supporting more than 2 terabytes of bandwidth, according to Su.

Lisa Su holds up prototype showing the exposed 3D V-Cache on the left CCD (Source: AMD/YouTube)

A production chip will provide 96 megabytes of cache per core complex die, for 192 megabytes total across 12 or 16 Ryzen cores in a single package, Su said.

Explaining the manufacturing process, she said, “We thinned the 3D cache die and added structural silicon to create a seamless surface for the combined chip. The finished 3D stacked version of the CPU actually looks exactly the same as a current Ryzen 5000 processors.”

The 3D chiplet technology is on track for production by the end of this year, starting with the company’s “highest end products,” Su said.

“Our first application of 3D chiplet technology at Computex demonstrates our commitment to continue pushing the envelope in high-performance computing to significantly enhance user experiences,” Su said in a statement.

AMD did not disclose the specific products that would be debuting the technology, although there are rumors of a new CPU that will implement 3D chiplets, codenamed Milan-X.

The announcement builds on AMD’s innovative packaging advances, starting with the company’s introduction of 2.5D HBM in 2015, its debut of high-volume multi-chip module (MCM) packages in 2017 (Zen 1) and its launch of chiplets in 2019 (Zen 2), enabling I/O to be on a different process than the compute cores.

Prime competitor Intel has been focusing on packaging advances as well. Intel took a page from AMD when it rolled out its 56-core Cascade Lake-AP chip in 2019, which brought together two dies in a multi-chip module. For its upcoming Xe GPU line, Intel is introducing a tile approach that allows different elements made by different manufacturers to be integrated into a single package, leveraging Intel’s Foveros and EMIB technologies.

Intel’s Raja Koduri said in March that Intel “switch[ed] to ’tile’ nomenclature to differentiate silicon that needs to be packaged with advanced high density packaging (55 micron bump pitches and below) [versus] silicon ‘chiplets’ that can be packaged with standard packaging.”

During its Computex activities, Intel said that its fourth-generation Xeon Scalable processor, the 10nm Sapphire Rapids, will launch in the first half of 2022. In a statement provided to HPCwire, Intel said: “Sapphire Rapids…is scheduled to reach production around the end of 2021 and ramp in the first half of 2022.” Sapphire Rapids is part of the Aurora supercomputer design, the latest iteration of which was originally slated to arrive at Argonne inside 2021. However, the exascale-class machine was delayed to 2022 due to Intel’s 7nm node slip that impacted the schedule for the Ponte Vecchio GPU, which will provide the system with most of its performance.

The other two planned U.S. exascale systems – Frontier at Oak Ridge and El Capitan at Livermore – will be powered by AMD technology. Along with next-generation AMD Instinct GPUs, Frontier (slated to arrive at Oak Ridge later this year) is expected to leverage a custom AMD third-generation Epyc processor. Perhaps the rumored Milan-X (or another custom Milan chip) will debut in Frontier with AMD’s new 3D V-Cache technology.

At least one HPC watcher we spoke with was enthusiastic about AMD’s 3D chiplet news.

“The planned advancements for AMD into 3D chiplets are extremely relevant for HPC applications, which continue to chase performance gains in both computation and memory,” said Addison Snell, CEO and founder of Intersect360 Research. “AMD’s almost monomaniacal focus on performance is particularly interesting in context with its competition, and Intel also announced that the Sapphire Rapids CPU will not be ready for general availability this year.”

Editor’s note: this article originally reported that Intel’s Sapphire Rapids chip launch had been delayed from late 2021 into the first half of 2022. Intel reports that there has been no change to the schedule. The article has been updated to reflect that.

Intel’s full official statement on the matter: “We have not slipped our Sapphire Rapids schedule and there is no change to the timing of Sapphire Rapids. It is scheduled to reach production around the end of 2021 and ramp in the first half of 2022. For our data center products it is common to have a formal product launch after the product has been shipping to customers for some time, and closer to broader customer availability.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

What’s After Exascale? The Internet of Workflows Says HPE’s Nicolas Dubé

July 29, 2021

With the race to exascale computing in its final leg, it’s natural to wonder what the Post Exascale Era will look like. Nicolas Dubé, VP and chief technologist for HPE’s HPC business unit, agrees and shared his vision at Supercomputing Frontiers Europe 2021 held last week. The next big thing, he told the virtual audience at SFE21, is something that will connect HPC and (broadly) all of IT – into what Dubé calls The Internet of Workflows. Read more…

How UK Scientists Developed Transformative, HPC-Powered Coronavirus Sequencing System

July 29, 2021

In November 2020, the COVID-19 Genomics UK Consortium (COG-UK) won the HPCwire Readers’ Choice Award for Best HPC Collaboration for its CLIMB-COVID sequencing project. Launched in March 2020, CLIMB-COVID has now resulted in the sequencing of over 675,000 coronavirus genomes – an increasingly critical task as variants like Delta threaten the tenuous prospect of a return to normalcy in much of the world. Read more…

KAUST Leverages Mixed Precision for Geospatial Data

July 28, 2021

For many computationally intensive tasks, exacting precision is not necessary for every step of the entire task to obtain a suitably precise result. The alternative is mixed-precision computing: using high precision wher Read more…

Oak Ridge Supercomputer Enables Next-Gen Jet Turbine Research

July 27, 2021

Air travel is notoriously carbon-inefficient, with many airlines going as far as to offer purchasable carbon offsets to ease the guilt over large-footprint travel. But even over just the last decade, major aircraft model Read more…

IBM and University of Tokyo Roll Out Quantum System One in Japan

July 27, 2021

IBM and the University of Tokyo today unveiled an IBM Quantum System One as part of the IBM-Japan quantum program announced in 2019. The system is the second IBM Quantum System One assembled outside the U.S. and follows Read more…

AWS Solution Channel

Data compression with increased performance and lower costs

Many customers associate a performance cost with data compression, but that’s not the case with Amazon FSx for Lustre. With FSx for Lustre, data compression reduces storage costs and increases aggregate file system throughput. Read more…

Intel Unveils New Node Names; Sapphire Rapids Is Now an ‘Intel 7’ CPU

July 27, 2021

What's a preeminent chip company to do when its process node technology lags the competition by (roughly) one generation, but outmoded naming conventions make it seem like it's two nodes behind? For Intel, the response was to change how it refers to its nodes with the aim of better reflecting its positioning within the leadership semiconductor manufacturing space. Intel revealed its new node nomenclature, and... Read more…

What’s After Exascale? The Internet of Workflows Says HPE’s Nicolas Dubé

July 29, 2021

With the race to exascale computing in its final leg, it’s natural to wonder what the Post Exascale Era will look like. Nicolas Dubé, VP and chief technologist for HPE’s HPC business unit, agrees and shared his vision at Supercomputing Frontiers Europe 2021 held last week. The next big thing, he told the virtual audience at SFE21, is something that will connect HPC and (broadly) all of IT – into what Dubé calls The Internet of Workflows. Read more…

How UK Scientists Developed Transformative, HPC-Powered Coronavirus Sequencing System

July 29, 2021

In November 2020, the COVID-19 Genomics UK Consortium (COG-UK) won the HPCwire Readers’ Choice Award for Best HPC Collaboration for its CLIMB-COVID sequencing project. Launched in March 2020, CLIMB-COVID has now resulted in the sequencing of over 675,000 coronavirus genomes – an increasingly critical task as variants like Delta threaten the tenuous prospect of a return to normalcy in much of the world. Read more…

IBM and University of Tokyo Roll Out Quantum System One in Japan

July 27, 2021

IBM and the University of Tokyo today unveiled an IBM Quantum System One as part of the IBM-Japan quantum program announced in 2019. The system is the second IB Read more…

Intel Unveils New Node Names; Sapphire Rapids Is Now an ‘Intel 7’ CPU

July 27, 2021

What's a preeminent chip company to do when its process node technology lags the competition by (roughly) one generation, but outmoded naming conventions make it seem like it's two nodes behind? For Intel, the response was to change how it refers to its nodes with the aim of better reflecting its positioning within the leadership semiconductor manufacturing space. Intel revealed its new node nomenclature, and... Read more…

Will Approximation Drive Post-Moore’s Law HPC Gains?

July 26, 2021

“Hardware-based improvements are going to get more and more difficult,” said Neil Thompson, an innovation scholar at MIT’s Computer Science and Artificial Intelligence Lab (CSAIL). “I think that’s something that this crowd will probably, actually, be already familiar with.” Thompson, speaking... Read more…

With New Owner and New Roadmap, an Independent Omni-Path Is Staging a Comeback

July 23, 2021

Put on a shelf by Intel in 2019, Omni-Path faced a uncertain future, but under new custodian Cornelis Networks, OmniPath is looking to make a comeback as an independent high-performance interconnect solution. A "significant refresh" – called Omni-Path Express – is coming later this year according to the company. Cornelis Networks formed last September as a spinout of Intel's Omni-Path division. Read more…

Chameleon’s HPC Testbed Sharpens Its Edge, Presses ‘Replay’

July 22, 2021

“One way of saying what I do for a living is to say that I develop scientific instruments,” said Kate Keahey, a senior fellow at the University of Chicago a Read more…

Summer Reading: “High-Performance Computing Is at an Inflection Point”

July 21, 2021

At last month’s 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), a group of researchers led by Martin Schulz of the Leibniz Supercomputing Center (Munich) presented a “position paper” in which they argue HPC architectural landscape... Read more…

AMD Chipmaker TSMC to Use AMD Chips for Chipmaking

May 8, 2021

TSMC has tapped AMD to support its major manufacturing and R&D workloads. AMD will provide its Epyc Rome 7702P CPUs – with 64 cores operating at a base cl Read more…

Intel Launches 10nm ‘Ice Lake’ Datacenter CPU with Up to 40 Cores

April 6, 2021

The wait is over. Today Intel officially launched its 10nm datacenter CPU, the third-generation Intel Xeon Scalable processor, codenamed Ice Lake. With up to 40 Read more…

Berkeley Lab Debuts Perlmutter, World’s Fastest AI Supercomputer

May 27, 2021

A ribbon-cutting ceremony held virtually at Berkeley Lab's National Energy Research Scientific Computing Center (NERSC) today marked the official launch of Perlmutter – aka NERSC-9 – the GPU-accelerated supercomputer built by HPE in partnership with Nvidia and AMD. Read more…

Ahead of ‘Dojo,’ Tesla Reveals Its Massive Precursor Supercomputer

June 22, 2021

In spring 2019, Tesla made cryptic reference to a project called Dojo, a “super-powerful training computer” for video data processing. Then, in summer 2020, Tesla CEO Elon Musk tweeted: “Tesla is developing a [neural network] training computer called Dojo to process truly vast amounts of video data. It’s a beast! … A truly useful exaflop at de facto FP32.” Read more…

Google Launches TPU v4 AI Chips

May 20, 2021

Google CEO Sundar Pichai spoke for only one minute and 42 seconds about the company’s latest TPU v4 Tensor Processing Units during his keynote at the Google I Read more…

CentOS Replacement Rocky Linux Is Now in GA and Under Independent Control

June 21, 2021

The Rocky Enterprise Software Foundation (RESF) is announcing the general availability of Rocky Linux, release 8.4, designed as a drop-in replacement for the soon-to-be discontinued CentOS. The GA release is launching six-and-a-half months after Red Hat deprecated its support for the widely popular, free CentOS server operating system. The Rocky Linux development effort... Read more…

CERN Is Betting Big on Exascale

April 1, 2021

The European Organization for Nuclear Research (CERN) involves 23 countries, 15,000 researchers, billions of dollars a year, and the biggest machine in the worl Read more…

Iran Gains HPC Capabilities with Launch of ‘Simorgh’ Supercomputer

May 18, 2021

Iran is said to be developing domestic supercomputing technology to advance the processing of scientific, economic, political and military data, and to strengthen the nation’s position in the age of AI and big data. On Sunday, Iran unveiled the Simorgh supercomputer, which will deliver.... Read more…

Leading Solution Providers

Contributors

HPE Launches Storage Line Loaded with IBM’s Spectrum Scale File System

April 6, 2021

HPE today launched a new family of storage solutions bundled with IBM’s Spectrum Scale Erasure Code Edition parallel file system (description below) and featu Read more…

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

GTC21: Nvidia Launches cuQuantum; Dips a Toe in Quantum Computing

April 13, 2021

Yesterday Nvidia officially dipped a toe into quantum computing with the launch of cuQuantum SDK, a development platform for simulating quantum circuits on GPU-accelerated systems. As Nvidia CEO Jensen Huang emphasized in his keynote, Nvidia doesn’t plan to build... Read more…

Microsoft to Provide World’s Most Powerful Weather & Climate Supercomputer for UK’s Met Office

April 22, 2021

More than 14 months ago, the UK government announced plans to invest £1.2 billion ($1.56 billion) into weather and climate supercomputing, including procuremen Read more…

Quantum Roundup: IBM, Rigetti, Phasecraft, Oxford QC, China, and More

July 13, 2021

IBM yesterday announced a proof for a quantum ML algorithm. A week ago, it unveiled a new topology for its quantum processors. Last Friday, the Technical Univer Read more…

Q&A with Jim Keller, CTO of Tenstorrent, and an HPCwire Person to Watch in 2021

April 22, 2021

As part of our HPCwire Person to Watch series, we are happy to present our interview with Jim Keller, president and chief technology officer of Tenstorrent. One of the top chip architects of our time, Keller has had an impactful career. Read more…

Senate Debate on Bill to Remake NSF – the Endless Frontier Act – Begins

May 18, 2021

The U.S. Senate today opened floor debate on the Endless Frontier Act which seeks to remake and expand the National Science Foundation by creating a technology Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire