At Computex 2021, held virtually this week, AMD showcased a new 3D chiplet architecture that will be used for future high-performance computing products set to debut later this year. AMD said it’s been working closely with semiconductor partner TSMC over the last few years to combine chiplet packaging with die stacking to develop the new technology.
The first application of the 3D chiplet is 3D vertical cache (3D V-Cache). To demonstrate the technology, AMD created a prototype by bonding a 3D vertical cache onto an AMD Ryzen 5000 series processor. AMD’s hybrid bond approach with through-silicon vias (TSVs) provides over 200 times the interconnect density of 2D chiplets and more than 15 times the density compared to existing vertical stacking solutions, according to the company. “This enables a much more efficient and denser integration of our IP,” said AMD CEO Lisa Su.
In a comparison demo against AMD’s fastest gaming CPU, the Ryzen 9 5900X, the prototype Ryzen 5900X with 3D V-Cache attached delivered a 12 percent higher frame rate for Xbox Game Studios’ game Gears 5. In benchmarking on five other games, performance increased an average of 15 percent using the 3D V-Cache technology.
The die-to-die interface uses a direct copper-to-copper bond with no solder bumps, said Su. “This approach improves the thermals, the transistor density and interconnect pitch, and it’s only one-third the energy per signal of micro-bump 3D approaches,” Su said. “All of these things make this truly the most advanced and flexible active-on-active silicon stacking technology in the world.”
For the Ryzen 5000 series prototype (show below), AMD stacked a 64MB 7nm SRAM directly on top of each core complex, tripling the L3 cache available to the Zen 3 cores. The through-silicon vias pass signals and power between the stacked chips, supporting more than 2 terabytes of bandwidth, according to Su.
A production chip will provide 96 megabytes of cache per core complex die, for 192 megabytes total across 12 or 16 Ryzen cores in a single package, Su said.
Explaining the manufacturing process, she said, “We thinned the 3D cache die and added structural silicon to create a seamless surface for the combined chip. The finished 3D stacked version of the CPU actually looks exactly the same as a current Ryzen 5000 processors.”
The 3D chiplet technology is on track for production by the end of this year, starting with the company’s “highest end products,” Su said.
“Our first application of 3D chiplet technology at Computex demonstrates our commitment to continue pushing the envelope in high-performance computing to significantly enhance user experiences,” Su said in a statement.
AMD did not disclose the specific products that would be debuting the technology, although there are rumors of a new CPU that will implement 3D chiplets, codenamed Milan-X.
The announcement builds on AMD’s innovative packaging advances, starting with the company’s introduction of 2.5D HBM in 2015, its debut of high-volume multi-chip module (MCM) packages in 2017 (Zen 1) and its launch of chiplets in 2019 (Zen 2), enabling I/O to be on a different process than the compute cores.
Prime competitor Intel has been focusing on packaging advances as well. Intel took a page from AMD when it rolled out its 56-core Cascade Lake-AP chip in 2019, which brought together two dies in a multi-chip module. For its upcoming Xe GPU line, Intel is introducing a tile approach that allows different elements made by different manufacturers to be integrated into a single package, leveraging Intel’s Foveros and EMIB technologies.
Intel’s Raja Koduri said in March that Intel “switch[ed] to ’tile’ nomenclature to differentiate silicon that needs to be packaged with advanced high density packaging (55 micron bump pitches and below) [versus] silicon ‘chiplets’ that can be packaged with standard packaging.”
During its Computex activities, Intel said that its fourth-generation Xeon Scalable processor, the 10nm Sapphire Rapids, will launch in the first half of 2022. In a statement provided to HPCwire, Intel said: “Sapphire Rapids…is scheduled to reach production around the end of 2021 and ramp in the first half of 2022.” Sapphire Rapids is part of the Aurora supercomputer design, the latest iteration of which was originally slated to arrive at Argonne inside 2021. However, the exascale-class machine was delayed to 2022 due to Intel’s 7nm node slip that impacted the schedule for the Ponte Vecchio GPU, which will provide the system with most of its performance.
The other two planned U.S. exascale systems – Frontier at Oak Ridge and El Capitan at Livermore – will be powered by AMD technology. Along with next-generation AMD Instinct GPUs, Frontier (slated to arrive at Oak Ridge later this year) is expected to leverage a custom AMD third-generation Epyc processor. Perhaps the rumored Milan-X (or another custom Milan chip) will debut in Frontier with AMD’s new 3D V-Cache technology.
At least one HPC watcher we spoke with was enthusiastic about AMD’s 3D chiplet news.
“The planned advancements for AMD into 3D chiplets are extremely relevant for HPC applications, which continue to chase performance gains in both computation and memory,” said Addison Snell, CEO and founder of Intersect360 Research. “AMD’s almost monomaniacal focus on performance is particularly interesting in context with its competition, and Intel also announced that the Sapphire Rapids CPU will not be ready for general availability this year.”
Editor’s note: this article originally reported that Intel’s Sapphire Rapids chip launch had been delayed from late 2021 into the first half of 2022. Intel reports that there has been no change to the schedule. The article has been updated to reflect that.
Intel’s full official statement on the matter: “We have not slipped our Sapphire Rapids schedule and there is no change to the timing of Sapphire Rapids. It is scheduled to reach production around the end of 2021 and ramp in the first half of 2022. For our data center products it is common to have a formal product launch after the product has been shipping to customers for some time, and closer to broader customer availability.”