Moore’s law is in decline due to the physical limits of transistor chips, putting an expiration date on a hitherto-perennial exponential trend in computing power – and leaving hardware developers scrambling to continue delivering similarly impressive improvements amid increasingly difficult engineering challenges. Now, researchers at Pacific Northwest National Laboratory (PNNL) have developed a new tool, called OpenCGRA, to help speed the development of faster chip architectures.
Specifically, OpenCGRA accelerates the development of chip architectures based on coarse-grained reconfigurable arrays (CGRAs) – hence the name. CGRAs, which are a type of hardware accelerator, combine the flexibility of CPUs with the efficiency of application-specific integrated circuits (ASICs). They handle resource-heavy applications (like machine learning) particularly well, but the rapid iteration in those algorithms demands a punishingly rapid pace on the hardware side, as well.
That’s where OpenCGRA comes in: the software models, validates and evaluates CGRA models, drastically reducing the timeframe for hardware design – and, in particular, individualized hardware design for a user’s specific needs. These individualized chips, thanks to the flexibility inherent in CGRAs, would still be manufacturable without the cost-prohibitive need for specialized fabrication facilities.
“By using OpenCGRA, it only takes a few hours to build a specialized power- and area-efficient CGRA throughout the entire design flow given a set of applications of interest,” the authors wrote in their paper.
The researchers hope that OpenCGRA could help make CGRAs a force to be reckoned with in chip design. Further, they anticipate that the hardware-software codesign element of CGRAs strengthens the bond between domain experts and computer scientists and makes those collaborations easier to translate into hardware.
“OpenCGRA helps domain science researchers collaborate with computer scientists to develop potential CGRAs from top-level models to hardware designs,” said Cheng Tan, a computer scientist at PNNL lead author of the study, in an interview with PNNL’s Sarah Wong.
“OpenCGRA represents a breakthrough in the push to open hardware design tools to a wider population of computer scientists, putting the power of purpose-designed computing architectures into the hands of users,” added Kevin Barker, who is also a computer scientist at PNNL and who co-authored the study.
The research discussed in this article was published as “OpenCGRA: An Open-Source Unified Framework for Modeling, Testing, and Evaluating CGRAs” in the proceedings of the 2020 IEEE 38th International Conference on Computer Design. The paper was written by Cheng Tan, Chenhao Xie, Ang Li, Kevin J. Barker and Antonino Tumeo. The paper is available here, while the OpenCGRA tool itself is available here.