In this video interview with HPCwire’s Managing Editor Tiffany Trader, Jean-Marc Denis, European Processor Initiative (EPI) chair of the board and head of strategy at Atos, details ongoing EPI activities and covers themes from his upcoming ISC 2021 featured talk, titled “Future Supercomputers are game changers for processor architecture. Why?”
The European Processor Initiative (EPI) was established in late 2018 with the goal of helping the EU achieve independence in HPC technologies. The first-generation chip family, named Rhea, is based on Arm’s Neoverse V1 core. Made by SiPearl, Rhea is slated for use in the forthcoming European exascale supercomputer in 2023. EPI is also developing RISC-V based processors and recently taped out test chips. The Rhea chip employs 29 RISC-V cores for non-compute support functions.
Here are highlighted excerpts from the interview:
EPI’s embrace of Arm and RISC-V…
[Rhea] is the technology that will be in the European exascale supercomputers in 2023. But we don’t only have this first microprocessor on our roadmap. Obviously we are thinking about the second generation. And we’ve started thinking also about the third generation. But from the long-term objective we have set, having over the decade our own technology based on RISC-V, while we don’t have products to to announce yet, we already are testing our own technology in 22 nanometer on a test chip, where we are going to prove that the key IPs that we are developing based on RISC-V can work. And we are announcing with Barcelona Supercomputing Center that some of the key IP has been taped out and will be available in the next months to prove the quality of the technology.
We have a lot of expectations for the next year or so around what we are doing on EPI complementary with RISC-V in our first step, and then later on, we will slowly switch from Arm to RISC-V. But don’t get me wrong: the fact that Rhea, the first microprocessor, is based on Arm Neoverse V1 doesn’t mean there is no RISC-V inside, we already have many RISC-V elements and IP in the Rhea microprocessors. For instance, in Rhea, we have 29 RISC-V cores on the chip, not for computing, but for different components that we need for making the chip efficient and working well for program management, traffic management, and so on. So we already have a smart combination of Arm technology with RISC-V technology.
This is why I don’t think that when people claim there is some kind of opposition or fight between our Arm or RISC-V, this this is appropriate, because it’s totally complementary. And the most efficient way to work is the one we have chosen: this is to combine both in the same developments and in the same products.
Next steps for EPI…
To prove with the RISC-V test chip at first. And the highest level step is to deliver the Rhea microprocessor on time for the European exascale supercomputers. So I would say this is very operational, very concrete. We are also preparing in parallel the second financial round of the European Processor Initiative. We are finalizing that with EuroHPC. We will start the second financial round of EPI, in November of this year, for the second generation of general purpose processor and with complex RISC-V components, likely in accelerators.
Not just for HPC; serving broader markets…
If we just develop for HPC that will be a fantastic technology showcase but there will be no business consequence on the long term. HPC on its own is not large enough for developing a very complex microprocessor with the crazy cost of developing in 5 nanometers on the future 3 nanometers or even below. So we need to have a side market, more business oriented, more volume loyalty, where we can produce very significant volume of microprocessors to make the economical model sustainable over time. So, when we launched the EPI, we thought that autonomous vehicles not only automotive, but autonomous vehicles, could be a great side market with millions of humans. But over time, we, we are seeing the complexity for developing such devices in terms of security, in terms of safety, in terms of other governmental constraints, of power consumption, on which we observe that the edge market is growing, is not great, is booming. It’s becoming a massive market. So by chance, what we started to develop with the automotive autonomous vehicle market can be reused, almost with no change for the edge market or more specifically for the infrastructure edge market on for datacenter. So now, for the next years, the focus in terms of business for volume will be much more or infrastructure edge and on datacenter.
The coming age of modularity and how to address the complexity…
I believe that the the era of monolithic machines, like the ones that we are going to see in the big labs, the U.S. is behind us. This is fantastic architecture and fantastic machines, don’t get me wrong, I’m not saying it’s bad. But it’s monolithic in the sense that all compute nodes in the machine are the same. Okay, it’s heterogeneous inside the node with a CPU and and accelerator, likely a GPU, it’s a SOC and so on, but the machine is really homogeneous. And I believe that with the evolution of high performance computing with the the mix of classical HPC algorithms with artificial intelligence, so theoretical models combined with experimental models, equations with data — we are moving full speed to workflows and to data flows, because there will be more and more data coming from IoT, coming from edge. There will be also hybrid computing with in-house computing combined with cloud computing from AWS from Microsoft Azure on so on. So, supercomputer operators have to combine all of them together. So, should one SOC on one machine on one compute node address all needs? No way. I don’t believe that at all.
I believe that at first the European exascale machines and the future post exascale machines will be modular, that will be a collection of different modules, each of them being homogeneous, but the machine as a whole will be a complete combination of totally different modules addressing the different stages or the different steps in the workflow or in the data flow. You could have a general purpose module with explicitly general-purpose processors, you could have a module containing a CPU with a GPU, another one CPU with FPGA, yet another one with a CPU on a neuromorphic device, and yet another one with a quantum accelerator, and so on and so forth. So, that would be very complex for supercomputer designers and operators and developers and end users, because they will have to manage all the different accelerators and CPU. So if we want to reduce the complexity, as a community, at least, we can plug the different accelerators to only one CPU model. So the one that will be, let’s say, the unification component for all the different accelerators.
And I’m claiming that the best way to have a single CPU is not to consider an instruction set. This is to consider the architecture of the CPU. It has to be, let’s say, a data hub, a massive data hub with many, many, many PCI Express or CXL lanes, with HBM, with DDR, and with a lot of flexibility to combine all of that together. Obviously, it has to address all the HPC applications that will never fit in accelerators, and there are many algorithms. And we have the legacy from the past; many applications have been developed over the last 40 years, even more. So should we move all the applications the tens of millions of lines of code to accelerators, I don’t believe that.
I believe that the CPU has to deliver good enough HPC performances, and it has to drive the many different accelerator classes that will be part of a modular architecture. So the global architecture will be modular; the CPU has to be a data integrator or data orchestrator for the many different accelerators and it has to be hybrid, it has to hybrid between in-house computing and cloud computing.
What the future holds…
I believe that the long-term direction will be toward Arm because we see today the cloud operators moving to Arm. We see what AWS has done with Graviton2. We see Ampere, that is becoming a very important in the cloud computing. We don’t know what’s going to be delivered by Microsoft, but maybe it could be with Arm as well. So Arm is becoming very important for cloud operators. And we also observe that in IoT, in edge computing, Arm is dominant. So to keep the complexity low, and to have a seamless data flow from IoT to cloud to supercomputers, I believe that the best way to go, at least for the next five years, will be to go with Arm — and then what’s beyond? I don’t know, I hope it’s going to be RISC-V because we are doing a lot around RISC-V in Europe for the future. But no one can predict what will be the future beyond let’s say 2026-2027.
Link to full video interview: https://www.youtube.com/watch?v=glhWLEVpScQ&feature=emb_logo
Also available as a This Week in HPC audio podcast: https://www.hpcwire.com/podcast/future-supercomputers-at-isc/