Intel Announces Sapphire Rapids with HBM, Reveals Ponte Vecchio Form Factors

By Tiffany Trader

June 28, 2021

From the ISC 2021 Digital event, Intel announced it will offer Sapphire Rapids with integrated HBM, detailed new Xe-HPC GPU form factors, and introduced commercial support for DAOS (distributed application object storage). Intel also announced a new Ethernet solution, aimed at smaller-scale HPC.

With integrated High Bandwidth Memory (HBM), the forthcoming Intel Xeon Scalable processors (codenamed “Sapphire Rapids”) will be a boon for HPC applications that operate memory bandwidth-sensitive workloads, Intel said. Applications will be able to leverage HBM alone or in combination with DDR5.

“Workloads such as modeling and simulation (e.g., computational fluid dynamics, climate and weather forecasting, quantum chromodynamics), artificial intelligence (e.g., deep learning training and inferencing), analytics (e.g., big data analytics), in-memory databases, storage and others power humanity’s scientific breakthroughs,” noted an Intel announcement.

In a media pre-briefing Intel’s vice president and general manager of HPC Trish Damkroger indicated Sapphire Rapids will be available ahead of Sapphire Rapids plus HBM (in the first half of 2022), but that they will come out in “roughly the same timeframe.” Announced wins for the HBM version include the Aurora supercomputer at Argonne National Laboratory and the Crossroads supercomputer at Los Alamos National Laboratory.

“Achieving results at exascale requires the rapid access and processing of massive amounts of data,” said Rick Stevens, associate laboratory director of Computing, Environment and Life Sciences at Argonne National Laboratory, in a statement. “Integrating high-bandwidth memory into Intel Xeon Scalable processors will significantly boost Aurora’s memory bandwidth and enable us to leverage the power of artificial intelligence and data analytics to perform advanced simulations and 3D modeling.”

“The Crossroads supercomputer at Los Alamos National Labs is designed to advance the study of complex physical systems for science and national security,” said Charlie Nakhleh, associate laboratory director for Weapons Physics at Los Alamos National Laboratory. “Intel’s next-generation Xeon processor Sapphire Rapids, coupled with High Bandwidth Memory, will significantly improve the performance of memory-intensive workloads in our Crossroads system. The [Sapphire Rapids with HBM] product accelerates the largest complex physics and engineering calculations, enabling us to complete major research and development responsibilities in global security, energy technologies and economic competitiveness.”

Sapphire Rapids implements new technologies DDR5, PCIe 5.0, and CXL 1.1, and it debuts built-in AI acceleration with Intel Advanced Matrix Extensions (AMX) for increased deep learning inference and training.

Momentum for Xe GPUs

Damkroger provided a progress report on Intel’s new server GPU “Xe” products, and said that the Xe-HPC Ponte Vecchio is powered on and is in the validation process.

“We have launched the Intel server graphics SG1, which is based on the Xe-LP, and we’re sampling DG2, which is based on Xe-HPG for enthusiasts, so those are getting out in the market today. And our Xe-HP based products are in Intel Dev Cloud and being used for software development,” Damkroger said.

Xe-HP is the ramp and software development vehicle for Intel’s Xe-HPC GPU, aka Ponte Vecchio, which is the underpinning of the future Aurora system, scheduled for delivery at Argonne National Lab next year.

Intel revealed that the mixed-process Ponte Vecchio GPU will be available in an OCP Accelerator Module (OAM) form factor and an Intel-branded four-way sub-system to serve the scale-out and scale-up capabilities required for HPC applications.


The Aurora system baseboards, meanwhile, are a custom design, implementing two Xeon Sapphire Rapids CPUs and six Ponte Vecchio GPUs, in a one to three ratio.

Supported DAOS; OneAPI

Intel is now offering commercial support for DAOS (distributed application object storage), an open-source software-defined object store that targets the exascale era. DAOS is at the foundation of the Intel Exascale storage stack, and is being used by Intel customers such as LRZ and JINR (Joint Institute for Nuclear Research). As well, DAOS will be the I/O backbone for the coming Aurora system.

Damkroger also highlighted the momentum for OneAPI and shared the virtual stage with Paul Calleja, director of research computing services at the University of Cambridge, where Intel has funded the Cambridge Open Exacale Lab. The lab is where researchers “collaborate on next-generation systems and can explore emerging technologies that will benefit not just the largest supercomputers but also HPC systems of all scales,” Calleja.

“Lab users can access our 10-petaflops system [Cambridge Service for Data Driven Discovery, or CSD3] to develop code for Intel GPUs using OneAPI, and get help optimizing applications for both CPUs and accelerators. They can also investigate extreme-scale storage systems, like Intel DAOS and work with cutting-edge high performance Ethernet fabrics,” said Calleja.

The University of Cambridge is also in the process of standing up a 600-node, ~2-petaflops system, based on Ice Lake technology, later this month.

DAOS Support and HPN Ethernet

Intel supports DAOS at the L3 level, enabling partners to provide a complete storage solution using Intel’s datacenter building blocks. Early DAOS support partners include HPE, Lenovo, Supermicro, Brightskies, Croit, Nettrix, Quanta and RSC Group.

Intel also announced a new High Performance Networking with Ethernet (HPN) solution, using the Tofino technology acquired through the acquisition of Barefoot Networks. HPN targets smaller clusters in the HPC segment, aiming to “enable application performance comparable to InfiniBand at a lower cost while taking advantage of the ease of use offered by Ethernet,” said Intel.

The solution leverages standard Intel Ethernet 800 Series Network Adapters and Controllers, switches based on Intel Tofino P4-programmable Ethernet switch ASICs and the Intel Ethernet Fabric suite software.

Intel on Top500

Intel’s 10nm Ice Lake processors debuted on the June 2021 Top500 list in eight systems with installations at Max-Planck, KIT, Korean Meteorological Administration, Osaka University and the University of Tokyo. While the Ice Lake Xeon platform offers up to 40 cores per processor, all eight Top500 systems are using the 36-core Ice Lake parts. Intel Xeon processors are used in the largest share (86.20 percent) of Top500 systems, down from 91.80 percent six months ago and 94 percent one year ago. 

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