Graphcore Launches Wafer-on-Wafer ‘Bow’ IPU

By Oliver Peckham

March 3, 2022

Graphcore introduced its AI-focused, PCIe-based Intelligent Processing Units (IPUs) six years ago. Since then, the company has done anything but slow down, announcing a second generation of IPUs in 2020 and, over the years, larger and larger IPU-based “IPU-POD” systems — most recently the IPU-POD128 and the IPU-POD256, both announced just a few months ago. Now, Graphcore is (quite literally) taking things to the next level, introducing its two-layer, wafer-on-wafer, third-generation IPU. Called “Bow,” the processor — which is shipping now — offers substantial improvements in performance and power efficiency over its predecessor. The company also announced plans for a massive system based on a forthcoming generation of its IPUs, which it is calling the Good computer.

Bow, WoW

The Bow IPU — so named after a London district, the new Graphcore naming convention — was manufactured using a new variant of TSMC’s 7nm process that enables wafer-on-wafer (WoW) packaging. “Wafer-on-wafer is a different technology to the chip-on-wafer vertical stacking that you might have seen, for example, with AMD’s Milan-X [which stacks] L3 cache on top of the processor,” explained Simon Knowles, co-founder, CTO and executive vice president for engineering at Graphcore. “Wafer-on-wafer is a more sophisticated technology. What it delivers is a much higher interconnect density between dies that are stacked on top of each other. As its name implies, it involves bonding wafers together before they are sawn. So two wafers are connected together — or in the future, more than two wafers — and then they are singulated into separate silicon chips.”

Click to view: a detailed diagram of Graphcore’s WoW structure for the Bow IPU. Image courtesy of Graphcore.

For Bow, Graphcore and TSMC attached a second wafer to the processor wafer, with the second wafer carrying a large number of deep-trench capacitor cells that allowed smoother power delivery to the device — which, in turn, enabled the processor to run faster and at a higher voltage. “This is just the first step for us,” Knowles said. “We have been working with TSMC to master this technology. We use it, initially, to build a better power supply for our processor — but it will go much further than that in the near future.”

Graphcore lauded TSMC, which, they said, had been working with them for 18 months on the Bow IPU. Graphcore is the first company to deliver wafer-on-wafer technology in a production product.

Thanks to the improved power delivery, Bow boasts up to a 40 percent improvement over its predecessor across major AI workloads, ranging from a 29 percent improvement at the low end of things (for an object detection workload) to a 39 percent improvement on the higher end for various NLP and image classification workloads. The Bow IPU is also up to 16 percent more power efficient.

The Bow IPU. Image courtesy of Graphcore.

Bow is, otherwise, relatively similar to the previous-gen IPU. “It has the same nearly 1GB of static RAM on the chip as the previous device, but now 40 percent faster access — so 65 terabytes-per-second access to nearly a gigabyte of on-chip memory,” Knowles said. “It has the same 1,472 independent processor cores, each capable of running six independent programs. … And finally, it has the same 10 IPU links to connect chips together, delivering, in total, 320 gigabytes per second of inter-chip bandwidth.”

The Bow IPU offers 350 peak teraflops of mixed-precision AI compute, or 87.5 peak single-precision teraflops. Graphcore noted that this compares favorably on paper to the listed peak for an Nvidia A100 (19.5 peak teraflops FP32), but real-world performance comparisons will, of course, be interesting to see.

IPU Machines & Bow Pods

Similarly to previous generations of Graphcore’s IPU, Bow gets packed (4×) into Bow-2000 IPU Machines, which offer 1.4 peak petaflops of AI compute (350 peak teraflops FP32). The Bow-2000s are then packed into Bow Pods of varying sizes, ranging from the Bow Pod16 (4× Bow-2000, 1.4 peak petaflops FP32) to the unprecedented Bow Pod1024 (256× Bow-2000, 89.6 peak petaflops FP32), which is currently in early access. (Graphcore also offers Pod32, Pod64 and Pod256 sizes.)

“These products all exist today and we are shipping to customers today,” said Nigel Toon, co-founder and CEO of Graphcore. Further, he said, there would be no increase in cost. (“We may choose to reduce the cost of [previous] systems — we haven’t made that announcement yet.”)

Toon compared the Bow Pod-16 (which he said retails for “just shy of $150,000”) to an Nvidia DGX A100 that retails for “just under $300,000.” The Bow Pod, he said, took 14 hours to train an efficient image classification model versus 17 hours on the Nvidia system. “That’s five times faster to train on a system that costs half the price.”

The Bow Pod16. Image courtesy of Graphcore.

All of this, Toon said, comes without painful adjustments for developers accustomed to Graphcore’s preceding products. “There are no code changes,” he assured. “So all of our existing models, all of our customers’ models that they built using our Poplar software environment, work seamlessly out of the box.”

And Graphcore has assembled an impressive list of customers for its third-generation products. The star of the show is Pacific Northwest National Laboratory (PNNL), which Graphcore says will be using these IPUs to help develop transformer-based and graph neural network models for computational chemistry and cybersecurity.

“At Pacific Northwest National Laboratory, we are pushing the boundaries of machine learning and graph neural networks to tackle scientific problems that have been intractable with existing technology,” said Sutanay Choudhury, co-director of PNNL’s Computational and Theoretical Chemistry Institute. “For instance, we are pursuing applications in computational chemistry and cybersecurity applications. This year, Graphcore systems have allowed us to significantly reduce both training and inference times from days to hours for these applications. This speed up shows promise in helping us incorporate the tools of machine learning into our research mission in meaningful ways. We look forward to extending our collaboration with this newest generation technology.”

Other major customers include Sandia National Laboratories, Imperial College London, the University of Massachusetts Amherst, the University of Oxford, Stanford Medicine and more — many of which the company said it could not name due to confidentiality.

The Good computer

But Graphcore isn’t stopping there. “When we started Graphcore, we talked about building the ‘Intelligence Processing Unit,’ so the idea has always been in the back of our mind to build an ultra-intelligence machine that would surpass the capability of a human brain — and that is what we are now working on,” Knowles said.

He clarified that they don’t know exactly what will be necessary for that dramatic goal — but that they can make some guesses. The human brain, he said, had around 100 billion neurons, plus axons with hundreds of trillions of synaptic weights; by comparison, today’s largest neural network models have around a trillion parameters.

“So we clearly have another two or three orders of magnitude to go before we might build a machine with the information capacity that clearly exceeds the human brain and therefore potentially unlocks ultra-intelligent AI,” he said. “Graphcore is intending — in fact, is on the path — to build such a machine.”

“This machine will contain 8,192 IPUs of a generation beyond the Bow processor, but further leveraging 3D wafer-on-wafer stacking technology,” he said, adding that the machine will deliver “over 10 exaflops” of floating-point performance and 4PB of memory, accessible at more than 10PB per second. “This will allow AI models to be hosted which are many hundreds of trillions of parameters.” (Graphcore specifically cites a goal of 500 trillion parameters.)

A rough outline of the Good computer. Image courtesy of Graphcore.

Knowles said that the Good computer is named after Jack Good, a 1960s computer scientist who “talked about the concept of an ultra-intelligence computer.” They clarified that the Good computer — which they expect to cost $120 million — will be a product intended for sale to multiple customers, not a one-off system.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

HPE Announces New HPC Factory in Czech Republic

May 18, 2022

A week ahead of ISC High Performance 2022 (set to be held in Hamburg, Germany), supercomputing heavyweight HPE has announced a major investment in sovereign European computing: its first European factory, housed in the C Read more…

Hyperion Study Tracks Rise and Impact of Linux Supercomputers

May 17, 2022

That supercomputers produce impactful, lasting value is a basic tenet among the HPC community. To make the point more formally, Hyperion Research has issued a new report, The Economic and Societal Benefits of Linux Super Read more…

ECP Director Doug Kothe Named ORNL Associate Laboratory Director

May 16, 2022

The Department of Energy's Oak Ridge National Laboratory (ORNL) has selected Doug Kothe to be the next Associate Laboratory Director for its Computing and Computational Sciences Directorate (CCSD), HPCwire has learned. K Read more…

Google Cloud’s New TPU v4 ML Hub Packs 9 Exaflops of AI

May 16, 2022

Almost exactly a year ago, Google launched its Tensor Processing Unit (TPU) v4 chips at Google I/O 2021, promising twice the performance compared to the TPU v3. At the time, Google CEO Sundar Pichai said that Google’s datacenters would “soon have dozens of TPU v4 Pods, many of which will be... Read more…

Q&A with Candace Culhane, SC22 General Chair and an HPCwire Person to Watch in 2022

May 14, 2022

HPCwire is pleased to present our interview with SC22 General Chair Candace Culhane, program/project director at Los Alamos National Lab and an HPCwire 2022 Person to Watch. In this exclusive Q&A, Culhane covers her Read more…

AWS Solution Channel

shutterstock 1103121086

Encoding workflow dependencies in AWS Batch

Most users of HPC or Batch systems need to analyze data with multiple operations to get meaningful results. That’s really driven by the nature of scientific research or engineering processes – it’s rare that a single task generates the insight you need. Read more…

Argonne Supercomputer Advances Energy Storage Research

May 13, 2022

The lack of large-scale energy storage bottlenecks many sources of renewable energy, such as sunlight-reliant solar power and unpredictable wind power. Researchers from Lawrence Livermore National Laboratory (LLNL) are w Read more…

HPE Announces New HPC Factory in Czech Republic

May 18, 2022

A week ahead of ISC High Performance 2022 (set to be held in Hamburg, Germany), supercomputing heavyweight HPE has announced a major investment in sovereign Eur Read more…

Google Cloud’s New TPU v4 ML Hub Packs 9 Exaflops of AI

May 16, 2022

Almost exactly a year ago, Google launched its Tensor Processing Unit (TPU) v4 chips at Google I/O 2021, promising twice the performance compared to the TPU v3. At the time, Google CEO Sundar Pichai said that Google’s datacenters would “soon have dozens of TPU v4 Pods, many of which will be... Read more…

Q&A with Candace Culhane, SC22 General Chair and an HPCwire Person to Watch in 2022

May 14, 2022

HPCwire is pleased to present our interview with SC22 General Chair Candace Culhane, program/project director at Los Alamos National Lab and an HPCwire 2022 Per Read more…

Supercomputing an Image of Our Galaxy’s Supermassive Black Hole

May 13, 2022

A supermassive black hole called Sagittarius A* (yes, the asterisk is part of it!) sits at the center of the Milky Way. Now, for the first time, we can see it. Read more…

Royalty-free stock illustration ID: 1919750255

Intel Says UCIe to Outpace PCIe in Speed Race

May 11, 2022

Intel has shared more details on a new interconnect that is the foundation of the company’s long-term plan for x86, Arm and RISC-V architectures to co-exist in a single chip package. The semiconductor company is taking a modular approach to chip design with the option for customers to cram computing blocks such as CPUs, GPUs and AI accelerators inside a single chip package. Read more…

Intel Extends IPU Roadmap Through 2026

May 10, 2022

Intel is extending its roadmap for infrastructure processors through 2026, the company said at its Vision conference being held in Grapevine, Texas. The company's IPUs (infrastructure processing units) are megachips that are designed to improve datacenter efficiency by offloading functions such as networking control, storage management and security that were traditionally... Read more…

Exascale Watch: Aurora Installation Underway, Now Open for Reservations

May 10, 2022

Installation has begun on the Aurora supercomputer, Rick Stevens (associate director of Argonne National Laboratory) revealed today during the Intel Vision event keynote taking place in Dallas, Texas, and online. Joining Intel exec Raja Koduri on stage, Stevens confirmed that the Aurora build is underway – a major development for a system that is projected to deliver more... Read more…

Intel’s Habana Labs Unveils Gaudi2, Greco AI Processors

May 10, 2022

At the hybrid Intel Vision event today, Intel’s Habana Labs team launched two major new products: Gaudi2, the second generation of the Gaudi deep learning training processor; and Greco, the successor to the Goya deep learning inference processor. Intel says that the processors offer significant speedups relative to their predecessors and the... Read more…

Nvidia R&D Chief on How AI is Improving Chip Design

April 18, 2022

Getting a glimpse into Nvidia’s R&D has become a regular feature of the spring GTC conference with Bill Dally, chief scientist and senior vice president of research, providing an overview of Nvidia’s R&D organization and a few details on current priorities. This year, Dally focused mostly on AI tools that Nvidia is both developing and using in-house to improve... Read more…

Royalty-free stock illustration ID: 1919750255

Intel Says UCIe to Outpace PCIe in Speed Race

May 11, 2022

Intel has shared more details on a new interconnect that is the foundation of the company’s long-term plan for x86, Arm and RISC-V architectures to co-exist in a single chip package. The semiconductor company is taking a modular approach to chip design with the option for customers to cram computing blocks such as CPUs, GPUs and AI accelerators inside a single chip package. Read more…

Facebook Parent Meta’s New AI Supercomputer Will Be ‘World’s Fastest’

January 24, 2022

Fresh off its rebrand last October, Meta (née Facebook) is putting muscle behind its vision of a metaversal future with a massive new AI supercomputer called the AI Research SuperCluster (RSC). Meta says that RSC will be used to help build new AI models, develop augmented reality tools, seamlessly analyze multimedia data and more. The supercomputer’s... Read more…

AMD/Xilinx Takes Aim at Nvidia with Improved VCK5000 Inferencing Card

March 8, 2022

AMD/Xilinx has released an improved version of its VCK5000 AI inferencing card along with a series of competitive benchmarks aimed directly at Nvidia’s GPU line. AMD says the new VCK5000 has 3x better performance than earlier versions and delivers 2x TCO over Nvidia T4. AMD also showed favorable benchmarks against several Nvidia GPUs, claiming its VCK5000 achieved... Read more…

In Partnership with IBM, Canada to Get Its First Universal Quantum Computer

February 3, 2022

IBM today announced it will deploy its first quantum computer in Canada, putting Canada on a short list of countries that will have access to an IBM Quantum Sys Read more…

Supercomputer Simulations Show How Paxlovid, Pfizer’s Covid Antiviral, Works

February 3, 2022

Just about a month ago, Pfizer scored its second huge win of the pandemic when the U.S. Food and Drug Administration issued another emergency use authorization Read more…

Nvidia Launches Hopper H100 GPU, New DGXs and Grace Superchips

March 22, 2022

The battle for datacenter dominance keeps getting hotter. Today, Nvidia kicked off its spring GTC event with new silicon, new software and a new supercomputer. Speaking from a virtual environment in the Nvidia Omniverse 3D collaboration and simulation platform, CEO Jensen Huang introduced the new Hopper GPU architecture and the H100 GPU... Read more…

PsiQuantum’s Path to 1 Million Qubits

April 21, 2022

PsiQuantum, founded in 2016 by four researchers with roots at Bristol University, Stanford University, and York University, is one of a few quantum computing startups that’s kept a moderately low PR profile. (That’s if you disregard the roughly $700 million in funding it has attracted.) The main reason is PsiQuantum has eschewed the clamorous public chase for... Read more…

Leading Solution Providers

Contributors

Nvidia Dominates MLPerf Inference, Qualcomm also Shines, Where’s Everybody Else?

April 6, 2022

MLCommons today released its latest MLPerf inferencing results, with another strong showing by Nvidia accelerators inside a diverse array of systems. Roughly fo Read more…

D-Wave to Go Public with SPAC Deal; Expects ~$1.6B Market Valuation

February 8, 2022

Quantum computing pioneer D-Wave today announced plans to go public via a SPAC (special purpose acquisition company) mechanism. D-Wave will merge with DPCM Capital in a transaction expected to produce $340 million in cash and result in a roughly $1.6 billion initial market valuation. The deal is expected to be completed in the second quarter of 2022 and the new company will be traded on the New York Stock... Read more…

Intel Announces Falcon Shores CPU-GPU Combo Architecture for 2024

February 18, 2022

Intel held its 2022 investor meeting yesterday, covering everything from the imminent Sapphire Rapids CPUs to the hotly anticipated (and delayed) Ponte Vecchio GPUs. But somewhat buried in its summary of the meeting was a new namedrop: “Falcon Shores,” described as “a new architecture that will bring x86 and Xe GPU together into a single socket.” The reveal was... Read more…

Industry Consortium Forms to Drive UCIe Chiplet Interconnect Standard

March 2, 2022

A new industry consortium aims to establish a die-to-die interconnect standard – Universal Chiplet Interconnect Express (UCIe) – in support of an open chipl Read more…

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

Nvidia Acquires Software-Defined Storage Provider Excelero

March 7, 2022

Nvidia has announced that it has acquired Excelero. The high-performance block storage provider, founded in 2014, will have its technology integrated into Nvidia’s enterprise software stack. Nvidia is not disclosing the value of the deal. Excelero’s core product, Excelero NVMesh, offers software-defined block storage via networked NVMe SSDs. NVMesh operates through... Read more…

India Launches Petascale ‘PARAM Ganga’ Supercomputer

March 8, 2022

Just a couple of weeks ago, the Indian government promised that it had five HPC systems in the final stages of installation and would launch nine new supercomputers this year. Now, it appears to be making good on that promise: the country’s National Supercomputing Mission (NSM) has announced the deployment of “PARAM Ganga” petascale supercomputer at Indian Institute of Technology (IIT)... Read more…

Google Launches TPU v4 AI Chips

May 20, 2021

Google CEO Sundar Pichai spoke for only one minute and 42 seconds about the company’s latest TPU v4 Tensor Processing Units during his keynote at the Google I Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire