AMD/Xilinx Takes Aim at Nvidia with Improved VCK5000 Inferencing Card

By John Russell

March 8, 2022

AMD/Xilinx has released an improved version of its VCK5000 AI inferencing card along with a series of competitive benchmarks aimed directly at Nvidia’s GPU line. AMD says the new VCK5000 has 3x better performance than earlier versions and delivers 2x TCO over Nvidia T4. AMD also showed favorable benchmarks against several Nvidia GPUs, claiming its VCK5000 achieved 90 percent of its true peak TOPS versus 34-to-42 percent for Nvidia’s A100, A30, A10, and T4 on “real AI model workloads.”

Taking such a strong stance, emphasizing TCO against Nvidia’s products is somewhat reminiscent of AMD’s strategy versus Intel in 2017 when AMD introduced the Epyc CPU line after a long absence from the datacenter. AMD, of course, just completed its acquisition of Xilinx last week having announced the deal back in 2020. The VCK5000 is available now for $2745 which AMD says is a very competitive price, particularly given “current supply chain issues.”

The company says it isn’t issuing a formal press release around the news, but it has been doing informal briefings such as one with HPCwire late last week.

“VCK5000 is the first PCIe card with our 7nm Versal ACAP silicon. It’s optimized for AI inference and this was the first time we are putting something from the AI engine core into the FPGA,” said Nick Ni, director of product marketing for AI and software solutions in AMD’s new Adaptive and Embedded Computing Group. “The card is actually not new, but what’s changed is we’ve improved the performance almost 3x on AI inferences. We’re also claiming we’re the world’s first zero dark silicon in AI inference – we’re the only ones who achieve near 100 percent the datasheet peak tops, which nobody else came close.”

The VCK5000 AI inferencing card includes FPGA and Arm CPU elements (see figure below) and was introduced last May. It’s part of AMD’s Versal Adaptive Compute Acceleration Platform (ACAP). The overall design, says AMD, solves what it calls the “dark silicon” problem – basically idle processing elements waiting for data from memory.

Analyst Steve Conway of Hyperion Research struck a cautious note. “Nvidia almost singlehandedly created the market for GPGPUs and dominates it today, but any large market will attract competitors and competition is a good thing. It’s too soon to know how competitive the new AMD/Xilinx inferencing card will be, but it’s great that more attention is being paid to inferencing. More capable inferencing adds intelligence to AI and should reduce the training burden for given tasks,” said Conway.

The HPC community may be more familiar with the Xilinx-Alveo U55C, which the company launched around SC21 and promoted as its most powerful FGPA-based accelerator card. Asked to distinguish between the two cards, AMD offered the following:

  • “The Alveo U55C falls within the AMD-Xilinx portfolio of production accelerator cards and is specifically targeted at HPC and big data workloads. It is based on the Virtex UltraScale+ FPGAs and is a different form factor compared to the VCK5000. With the Xilinx RoCE v2-based clustering solution, we’re enabling a broad spectrum of customers with large-scale compute workloads to implement powerful FPGA-based HPC clustering using their existing data center infrastructure and network.
  • “The VCK5000 is a development card based on the company’s 7nm Versal portfolio and is optimized for designs requiring high throughput AI inference and signal processing compute performance. The VCK5000 is the first AI chip to achieve near zero-dark silicon and beating competing devices like Nvidia’s A100 and T4 GPUs by up to 2x in performance/watt using standard benchmark models.”

A long-standing stumbling block to wider use of FPGAs has been their lengthy and complicated development process that requires programming at the RTL level. Both the Alveo U55C and VCK5000 cards attempt to skirt that challenge by leveraging AMD/Xilinx Vitis Unified Software Platform.

AMD/Xilinx VCK5000 Inference Card

Ni described the effort to program the newest VCK5000 to run the benchmarks: “So if you did a bottom-up design, a traditional design with RTL, [development] would have taken definitely longer compared to if you’re doing GPUs. But we use software abstraction [through Vitis]. All the results that we’re showing here did not involve any of the RTL development. Everything was just based on the TensorFlow, Pytorch. We basically took TensorFlow and ResNet 50 models provided by MLPerf into our compiler. You run it and you get the results. It’s really the same kind of design cycle as GPUs.”

Ni says the AMD/Xilinx will submit results for the VCK5000 in future MLPerf inference exercises.

It’s worth briefly noting that FPGA-based solutions have been gaining recent attention. Just yesterday Intel introduced the Agilex M-Series FPGAs built on the Intel 7 process. Intel reported the new FPGAs have: “the industry’s highest memory bandwidth for an FPGA; the industry’s highest DSP compute density in an HBM-enabled FPGA; and greater than 2X fabric performance per watt vs. competitive 7nm FPGAs.” Intel got into the FPGA game in 2015 with its acquisition of Altera.

The resurgence of interest in FPGAs has many causes including: the fast-growing size of AI models; the need to accelerate data movement in and out of these models; the continued evolution of software-defined architecture and the associated need for dispersed smart-controllers; and improving FPGA programming tools. Advocates argue that FPGA-based solutions offer a cost-effective blend of specialization and flexibility and performance. That’s always been the promise, but delivering it has frequently been challenging.

Now, FPGAs – both singly or paired with other processing and memory components and packaged as SoCs – are drawing attention. Vendors increasingly portray them as part of the AI-solution mix from datacenters to the edge.

AMD contends that unlike fixed-architecture GPUs, more flexible FPGA-based systems can be designed for the specific needs of AI models, in particular, the dataflow requirements. This argument is at the heart of AMD’s “solving the dark silicon” problem, which it says is keeping Nvidia GPUs well below 50 percent of the peak TOPS in some workflows.

“Because you have a fixed core AI processor, with Nvidia it’s for Tensor core GPUs, it’s designed for certain models and it’s fixed and also the data that has to be pumped into the engine to get the 100 percent efficiency. [When] you run today’s larger models, what happens is you create huge data bubbles (slide below) because you got to have a lot of cache misses in the shared cache. Even though the Nvidia A30 engine is capable of doing 330 TOPS, for example, they say only 40% of time you’re [getting] the data in. That’s where we need to get adaptable silicon [devices] such as FPGAs.

“What’s different about [the Xilinx approach] is two things. One is our engine. It’s as good as an ASIC, but we also have a little bit of programmability built-in. Within our VLIW cores, there’s also different types of data passing you can do, [for example] you can do broadcasting. But the most important thing is we are attaching FPGA fabric to that basic core. We are cache-less, we don’t even have a cache in the system so there’s no such thing as cache miss. You can create a perfect internal memory [flow] so you can pump the data every clock cycle into the engine. That’s really how you get 100 percent or near 100 percent efficiency out, [by] reducing the data bubble significant.”

Ni emphasized video analytics applications during the briefing and AMD/Xilinx does have a video analytics SDK and plug-in. But the platform is more flexible.

“We call it a domain specific architecture. Think of it as we carefully design very domain specific, in this case AI inference specific, FPGA programming that can run all these models. We didn’t want to make a one trick pony, right? We didn’t want to make IP that can only be Resnet50,” said Ni. The inference processing engine, he says, can have a secondary “small processor inside” that adjusts for different models based on compiled instructions.

AMD certainly has hopes for its portfolio of FPGA-based platforms.

When the deal closed, AMD CEO Lisa Su said, “The acquisition of Xilinx brings together a highly complementary set of products, customers and markets combined with differentiated IP and world-class talent to create the industry’s high-performance and adaptive computing leader. Xilinx offers industry-leading FPGAs, adaptive SOCs, AI engines and software expertise that enable AMD to offer the strongest portfolio of high-performance and adaptive computing solutions in the industry and capture a larger share of the approximately $135 billion market opportunity we see across cloud, edge and intelligent devices.”

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