Nvidia Launches Hopper H100 GPU, New DGXs and Grace Superchips

By Tiffany Trader

March 22, 2022

The battle for datacenter dominance keeps getting hotter. Today, Nvidia kicked off its spring GTC event with new silicon, new software and a new supercomputer. Speaking from a virtual environment in the Nvidia Omniverse 3D collaboration and simulation platform (adieu “kitchen keynote”), CEO Jensen Huang introduced the new Hopper GPU architecture and the H100 GPU, which will power datacenter-scale systems for HPC and AI workloads. 

Nvidia’s first Hopper-based product, the H100 GPU, is manufactured on TSMC’s 4N process, leveraging a whopping 80 billion transistors – 68 percent more than the prior-generation 7nm A100 GPU. The H100 is the first GPU to support PCIe Gen5 and the first to utilize HBM3, enabling 3TB/s of memory bandwidth. 

Named after computer scientist and U.S. Navy Rear Admiral Grace Hopper, the new GPU (in its SXM mezzanine form factor) provides 30 teraflops of peak standard IEEE FP64 performance, 60 teraflops of peak FP64 tensor core performance, and 60 teraflops of peak FP32 performance. A new numerical format introduced in Hopper, FP8 tensor core, delivers up to 4,000 theoretical teraflops of AI performance, according to Nvidia. See spec info and gen-to-gen comparisons below. 


Hopper introduces built-in acceleration for transformer models, which are widely used for natural language processing. The Hopper Transformer Engine dynamically chooses between 8-bit and 16-bit calculations, intelligently managing precision in the layers of the transformer network to deliver speedups without loss of accuracy, according to Nvidia.

“Hopper H100 is the biggest generational leap ever — 9x at-scale training performance over A100 and 30x large-language-model inference throughput,” Huang said in his keynote. 

Hopper’s second-generation Multi-Instance GPU (MIG) technology enables a single GPU to be partitioned into seven smaller, fully isolated instances. Hopper also introduces new DPX instructions that can be used by a number of algorithms, including route optimization and genomics to accelerate dynamic programming by 7x compared with previous-generation GPUs and 40x compared with CPUs, according to Nvidia. 

Hopper features new fourth-generation Nvidia NVLink technology, which for the first time extends outside the server in the form of the new NVLink Switch. The switch system connects up to 256 H100 GPUs (32-node DGX Pods) at 9x higher bandwidth versus the previous generation using Nvidia HDR Quantum InfiniBand. 

Nvidia H100 CNX converged accelerator. Credit: Nvidia

In addition to the SXM form factor that will be used inside DGX and HGX systems, Hopper will also be offered in an H100 PCIe form factor GPU, two of which can be linked via an NVLink bridge. Hopper will further be available as a new converged accelerator, the H100 CNX, that pairs the H100 with a ConnectX-7 SmartNIC, which both natively run PCIe Gen 5. The H100 CNX can be deployed in mainstream servers via the PCIe connection to the CPU.  “In the mainstream server with four GPUs, H100 CNX will boost the bandwidth to the GPU by four times and, at the same time, free up the CPU to process other parts of the application,” said Paresh Kharya, senior director of product management and marketing at Nvidia, in a pre-briefing held for media and analysts.

Charlie Boyle, vice president and general manager of DGX Systems at Nvidia, highlighted another benefit: being able to access the benefits of PCIe Gen 5 before the server products come to market. “The servers that you can buy today are still PCIe Gen 4, but with the combination H100 CNX card, it gives us the advantage of running full Gen 5 networking from the network directly to the GPU without involving the CPU. As the CNX cards are available, customers can upgrade to Hopper and get most of the advantage of the full PCIe Gen 5 system without actually needing to change their infrastructure waiting for the manufacturers to get to Gen 5,” Boyle said.

Nvidia Hopper H100 family. Credit: Nvidia

In tandem with the H100 launch, Nvidia is refreshing its DGX system architecture. The company’s fourth-generation DGX system, DGX H100, is powered by eight H100 GPUs that together provide 640GB of HBM3 with 3.6TB/s bisection bandwidth. NVSwitches with fourth-generation NVLink fabric connect the GPUs, providing 900GB/s connectivity, 1.5x more than the prior generation

An external NVLink Switch networks up to 32 DGX H100 nodes into Nvidia DGX Pod supercomputers, delivering up to 1 exaflops of AI performance leveraging the new DP8 tensor core units and up to 7.68 peak petaflops of standard IEEE FP64 performance. 

The DGX Pods can be scaled in 32-node increments to create even larger systems. Nvidia is showcasing the DGX H100 technology with another new in-house supercomputer, named Eos, which is scheduled to enter operations later this year. Eos, ostensibly named after the Greek goddess of the dawn, comprises 576 DGX H100 systems, 500 Quantum-2 InfiniBand systems and 360 NVLink switches. With 4,608 GPUs in total, Eos provides 18 exaflops of peak FP8 tensor core performance, 9 exaflops of peak FP16 tensor core performance and 138 petaflops of peak standard IEEE FP64 performance. Nvidia’s FP64 tensor core processing pushes peak HPC performance to 275 petaflops. See additional coverage on Eos here

The DGX H100 has a projected power consumption of ~10.2 kW max, which is about 1.6x higher than the DGX A100. This is on account of the higher thermal envelope for the H100, which draws up to 700 watts compared to the A100’s 400 watts. To accomodate the extra heat, Nvidia made the DGXs 2U taller, a design change that enables the boxes to still be air-cooled.

As with previous Nvidia GPUs, the H100 SXM will also be available in HGX H100 server boards with four- and eight-GPU configurations that will enable cloud providers and system-makers to build and offer their own H100 systems and clusters.

Nvidia H100 HGX baseboard. Credit: Nvidia

During the keynote, Huang shared a few more details about Nvidia’s upcoming Grace Arm CPU, and announced “Grace Superchips” in two form factors. The combined CPU+GPU SoC that was revealed last year now has an officially confirmed name: the Grace Hopper Superchip. Designed for giant-scale AI and HPC, the platform provides 600GB memory on the GPU and features a 900 gigabytes per second coherent interconnect, called NVLink chip-to-chip (C2C).

The CPU half of the Grace Hopper Superchip is the foundation of the Grace CPU Superchip. The discrete datacenter CPU comprises two Arm-based CPU chips coherently connected over the 900 gigabytes per second NVLink C2C interface to create a single-socket 144-core CPU with 1 terabyte-per-second of memory bandwidth. The Grace CPU Superchip offers a projected performance of 740 on the SPECrate2017_int_base benchmark, which Nvidia states is a 1.5x improvement over the performance of the two AMD CPUs shipping with the DGX A100 today. Nvidia further estimates that the Grace CPU Superchip – with a 500-watt TDP package inclusive of memory – will offer 2x the performance-per-watt of top-of-the-line CPUs when it ships. Both the Grace Hopper Superchip and the Grace CPU Superchip are scheduled to arrive in the first half of 2023. 

“The enabler for Grace Hopper and Grace Superchip is the ultra-energy-efficient, low-latency, high-speed memory-coherent NVLink C2C link,” said Huang. “With NVLink that scales from die-to-die, chip-to-chip and system-to-system, we can configure Grace and Hopper to address a large diversity of workloads [and create systems] with up to two Grace CPUs and eight Hopper GPUs.”

Nvidia announced that it is opening up NVLink C2C for custom silicon integrations. “Customers will be able to integrate and create Superchips with Nvidia just like we’ve created Grace Superchip and Grace Hopper Superchip,” said Kharya. “This die-to-die and chip-to-chip link will be available on future Nvidia GPUs, DPUs and CPUs to enable a new class of custom chips and systems. With dense packaging, Nvidia C2C provides 25 times higher energy efficiency and 90 times more area efficiency over the PCIe Gen 5 PHY on Nvidia chips,” he said.

Nvidia also announced that it will support the developing Universal Chiplet Interconnect Express (UCIe) standard, which launched earlier this month. Customers will be able to choose chip and system level integrations to connect to Nvidia chips. “For custom integrations, customers can use UCIe if they like and also NVLink C2C,” Kharya said.

DGX systems and H100 GPUs will begin shipping in the third quarter of this year, according to Nvidia. DGX pricing will be announced at a later date.

A wide range of partners are lining up to support the new H100 GPUs, Nvidia indicated. Planned instances are underway from Alibaba Cloud, Amazon Web Services, Baidu AI Cloud, Google Cloud, Microsoft Azure, Oracle Cloud and Tencent Cloud. While the list of systems companies on deck to build or integrate H100 platforms includes Atos, BOXX Technologies, Cisco, Dell Technologies, Fujitsu, Gigabyte, H3C, HPE, Inspur, Lenovo, Nettrix and Supermicro. 

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