Reflecting on the 25th Anniversary of ASCI Red and Continuing Themes for Our Heterogenous Future

By James Reinders

April 26, 2022

In the third of a series of guest posts on heterogeneous computing, James Reinders shares experiences surrounding the creation of ASCI Red and ties that system’s quadranscentennial anniversary to predictions about the heterogeneous future being ushered in by exaflops machines.

In 1997, ASCI Red appeared on the Top500 as the first teraflops machine in history. It held that spot for seven lists, a record that remains unbroken decades later. Using thousands of Intel microprocessors, it offered additional evidence that massively parallel machines based on “off the shelf” technology would dominate supercomputing of the future – a trend that was not universally endorsed in 1997. It was also not hard to find skeptics that claimed we would never need a petaflops of computing power, and many saw teraflops as only needed for military needs.

Twenty-five years later, exaflops machines offer evidence of trends that will dominate supercomputing of the future. Before I share my predictions of our future, I’ll reflect on how ASCI Red came to be.


In December 1996, while the machine was still at Intel in Oregon and only three-fourths built, ASCI Red ran for the first time above the one-trillion-operations-per-second rate.

The full system featured 1.2 TB of memory and 9,298 processors (200 MHz Intel Pentium Pro processor boosted later with specially packaged 333 MHz Pentium II Xeon processors) in 104 cabinets. Not including cooling, the system consumed 850 kW of power.

People speak of ASCI Red supercomputer, operated at Sandia for nine years, with a well-deserved reverence. Sandia director Bill Camp said, in 2006, that ASCI Red had the best reliability of any supercomputer ever built.

Why ASCI Red?

Accelerated Strategic Computing Initiative (ASCI), was a ten-year program designed to move nuclear weapons design and maintenance from a test-based (underground explosions) to simulation-based approach (no more underground testing).

By developing reliable computational models for the processes involved over the whole life of nuclear weapons, the U.S. could comfortably live with a Comprehensive Nuclear-Test-Ban Treaty. DOE scientists estimated they needed 100 teraflops by the early 2000s.

Convex, Tombstones, and Execution of Strategies

To build a teraflops machine it was initially believed we would need to do that with a non-Intel processor. Clearly, the floating-point performance of the Pentium processor was insufficient.

In 1994, I visited Convex Computer Corporation to consider if we should use HP processors. Convex pushed HP designs to their limits including over-clocking (long before gamers made this popular). On the patio just outside of the Convex cafeteria, there are more than twenty names etched in cement including Chopp Computer, ETA Systems, and Multiflow. These were all companies that started alongside Convex in supercomputers and failed as businesses.

They explained that these were reminders of the need for more than a great strategy and smart people, you have to actually execute it successfully. Convex cofounder Bob Paluck was quoted in Bloomberg as saying “You’ve got to have a brilliant strategy, and you have to actually execute it. Otherwise, you become a tombstone.”

It fits perfectly with the Andy Grove philosophy drilled into us at Intel that “only the paranoid survive.”

Convex survived and was eventually acquired by HP. While we didn’t select HP parts, I never forgot that Convex graveyard.

Krazy Glew on comp.arch

Intel was the first company to have hardware (the 8087 in 1980) supporting the (then draft) IEEE FP standard. The Intel i860 used a VLIW design to power the #1 supercomputer in 1994, but x86 floating-point remained disappointing for HPC. As a frequent reader of comp.arch on usenet, I was intrigued when Andy “Krazy” Glew from Intel’s P6 wrote “Don’t count Intel out on floating-point” to a flame about Intel floating point being noncompetitive. Andy and I hit it off.

I became the first champion in the architecture study team for using the P6 design. The interest became much greater when the first P6 parts — now called the Intel Pentium Pro — came back and it became apparent we could have 200MHz parts under 40 watts, and that included an on-package L2. The power efficiency, compute density, and costs quickly made it the obvious choice with the entire architecture team.

Comet Shoemaker–Levy 9 and C++

For the most part, C++ had no following in HPC. C++ was not an ANSI or ISO standard (that came in 1998). A notable exception was a group at Sandia, the destination for ASCI Red.

The discovery of Comet Shoemaker–Levy 9 and the realization that it was likely to collide with Jupiter caused great excitement – a never before seen opportunity to observe two significant Solar System bodies collide.

Astronomers and astrophysicists, with scant data to guide them, did not believe the effects of the collision would be visible from Earth. Sandia researchers, experts on high energy impacts, offered a different perspective. Computational simulations by Dave Crawford and Mark Boslough at Sandia, using C++ on an Intel Paragon supercomputer (#1 on the Top500 list at the time), predicted a visible plume rising above the rim of Jupiter. This public disagreement was carried by the media, notably CNN. In the end, the close correspondence between their predictions of a visible plume rising above the rim of Jupiter and the actual plume as observed by astronomers lent even more confidence to the accuracy of the Sandia simulation codes. What an awesome validation!

In a recent book “Impactful Times: Memories of 60 Years of Shock Wave Research at Sandia National Laboratories,” J. Michael McGlaun of Sandia related “We decided to write [c.1990] PCTH[1] in C++ rather than FORTRAN. We hoped to eliminate some coding errors using C++ features.” The results were “a version of PCTH working that demonstrated excellent parallel speedup” that also “demonstrated that we could eliminate many software defects in a carefully written C++ program.”

Sandia and comets helped fuel the interest that set the stage for C++ to really be a serious language on ASCI Red, in addition to the dominant FORTRAN and lesser used C.

Trends for the Future

In retrospect, most trends that would expand over the next twenty-five years were quite evident when you looked at what the needs were in 1997 and what results were coming out of groundbreaking work.

Those trends became even more evident during the life of ASCI Red. The spectacular comet simulations with C++ code was strong evidence of future directions (I can’t imagine writing an adaptive mesh code in Fortran no matter how much I love Fortran). While only defense uses were willing to pay for a teraflops machine, there were plenty of hints that would change including dual-use[2] work at Sandia. The insatiable appetite for performance drove the importance of standardizing message passing (MPI), and then the fattening of nodes with more and more computation at the node level which in turn fueled the need for node level standards (e.g., OpenMP). The topic of security has grown as well as the scope of usage has grown dramatically. Arguably, the least predictable trend was the giant leap in AI usefulness thanks to deep learning algorithms.

In brief, nine notable changes that went from small to big in the past twenty-five year are:

  1. The rise in importance of C++.
  2. The use of supercomputers for far more than military purposes.
  3. Standardization of MPI.
  4. Enormous growth of computational power at a node level (fat nodes).
  5. Standardization of OpenMP to help with fat node programming.
  6. Emergence of AI techniques as an important programming technique.
  7. Floating point accelerators (most notably GPUs) to boost performance/watt and density.
  8. Open source grew from occasional to ubiquitous.
  9. Security has grown from a local concern to one with many surfaces to worry about.

What would our next list look like twenty-five years from now after exaflops systems appear. We already should know that the following nine are in our future:

  1. More abstract programming – the rise in importance of Python, frameworks, and more and more abstractions to the point of inspiring thinking such as “No Code.”
  2. More uses – supercomputers democratized even more especially as cloud vendors offer supercomputing for all – another vote for abstractions and “No Code”?
  3. More programming attention for distributed computing – energized by higher performance interconnects.
  4. Heterogeneous computing – fatter nodes get even more diverse thanks to many solutions from multiple vendors plus the mix-and-match that will happen with open chiplet interconnect standards (“new golden age for computer architecture”).
  5. Multivendor multiarchitecture fat node programming – requires more open and performance portable solutions.
  6. Algorithms matter – emergence of more AI techniques (not just deep learning) as important.
  7. Multivendor heterogeneous capabilities to boost performance/watt and density – made more prevalent thanks to open chiplet interconnect standards.
  8. Open – continues to expand to support more competition in everything.
  9. Security – bigger machines, more simultaneous users, and wide availability make this an ever-growing topic of concern.

Unlike ASCI Red, our heterogeneous future will be multivendor, and multiarchitecture because competition is only growing in this “new golden age for computer architecture.”

Additionally, diversity in hardware demands that performance portability will be critical to the future. When systems were CPU-only, performance portability came about because each generation of CPUs sought to be uniformly better than the CPUs that came before. Every CPU tried to be general purpose. In a heterogeneous world, where specialization is needed for lower power and higher densities, non-CPU compute devices are no longer trying to be general purpose. Any rush to standardize in order to lock in the architectures of today will only serve to undermine the credibility of such a standard.

These nine trends demand we support more variety in hardware and applications, while making it more approachable, faster, and better.

And, unlike in 1997, we need to do it in far more than just Fortran (formerly known as FORTRAN).

“No code” is sounding better and better all the time. Dream on.

[1] PCTH stands for Parallel CTH, CTH stands for CSQ to the Three Halves, CSQ stands for CHARTD Squared, CHARTD stands for Coupled Hydrodynamics And Radiation Transport Diffusion). Learn more about CTH at

[2] Dual-use technologies refer to technologies with both military utility and commercial potential.

About the Author

James Reinders believes the full benefits of the evolution to full heterogeneous computing will be best realized with an open, multivendor, multiarchitecture approach. Reinders rejoined Intel a year ago, specifically because he believes Intel can meaningfully help realize this open future. Reinders is an author (or co-author and/or editor) of ten technical books related to parallel programming; his latest book is about SYCL (it can be freely downloaded here). 

Other articles in this series

Solving Heterogeneous Programming Challenges with SYCL

Why SYCL: Elephants in the SYCL Room

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

Quantum Watchers – Terrific Interview with Caltech’s John Preskill by CERN

July 17, 2024

In case you missed it, there's a fascinating interview with John Preskill, the prominent Caltech physicist and pioneering quantum computing researcher that was recently posted by CERN’s department of experimental physi Read more…

Aurora AI-Driven Atmosphere Model is 5,000x Faster Than Traditional Systems

July 16, 2024

While the onset of human-driven climate change brings with it many horrors, the increase in the frequency and strength of storms poses an enormous threat to communities across the globe. As climate change is warming ocea Read more…

Researchers Say Memory Bandwidth and NVLink Speeds in Hopper Not So Simple

July 15, 2024

Researchers measured the real-world bandwidth of Nvidia's Grace Hopper superchip, with the chip-to-chip interconnect results falling well short of theoretical claims. A paper published on July 10 by researchers in the U. Read more…

Belt-Tightening in Store for Most Federal FY25 Science Budets

July 15, 2024

If it’s summer, it’s federal budgeting time, not to mention an election year as well. There’s an excellent summary of the curent state of FY25 efforts reported in AIP’s policy FYI: Science Policy News. Belt-tight Read more…

Peter Shor Wins IEEE 2025 Shannon Award

July 15, 2024

Peter Shor, the MIT mathematician whose ‘Shor’s algorithm’ sent shivers of fear through the encryption community and helped galvanize ongoing efforts to build quantum computers, has been named the 2025 winner of th Read more…

Weekly Wire Roundup: July 8-July 12, 2024

July 12, 2024

HPC news can get pretty sleepy in June and July, but this week saw a bump in activity midweek as Americans realized they still had work to do after the previous holiday weekend. The world outside the United States also s Read more…

Aurora AI-Driven Atmosphere Model is 5,000x Faster Than Traditional Systems

July 16, 2024

While the onset of human-driven climate change brings with it many horrors, the increase in the frequency and strength of storms poses an enormous threat to com Read more…

Shutterstock 1886124835

Researchers Say Memory Bandwidth and NVLink Speeds in Hopper Not So Simple

July 15, 2024

Researchers measured the real-world bandwidth of Nvidia's Grace Hopper superchip, with the chip-to-chip interconnect results falling well short of theoretical c Read more…

Shutterstock 2203611339

NSF Issues Next Solicitation and More Detail on National Quantum Virtual Laboratory

July 10, 2024

After percolating for roughly a year, NSF has issued the next solicitation for the National Quantum Virtual Lab program — this one focused on design and imple Read more…

NCSA’s SEAS Team Keeps APACE of AlphaFold2

July 9, 2024

High-performance computing (HPC) can often be challenging for researchers to use because it requires expertise in working with large datasets, scaling the softw Read more…

Anders Jensen on Europe’s Plan for AI-optimized Supercomputers, Welcoming the UK, and More

July 8, 2024

The recent ISC24 conference in Hamburg showcased LUMI and other leadership-class supercomputers co-funded by the EuroHPC Joint Undertaking (JU), including three Read more…

Generative AI to Account for 1.5% of World’s Power Consumption by 2029

July 8, 2024

Generative AI will take on a larger chunk of the world's power consumption to keep up with the hefty hardware requirements to run applications. "AI chips repres Read more…

US Senators Propose $32 Billion in Annual AI Spending, but Critics Remain Unconvinced

July 5, 2024

Senate leader, Chuck Schumer, and three colleagues want the US government to spend at least $32 billion annually by 2026 for non-defense related AI systems.  T Read more…

Point and Click HPC: High-Performance Desktops

July 3, 2024

Recently, an interesting paper appeared on Arvix called Use Cases for High-Performance Research Desktops. To be clear, the term desktop in this context does not Read more…

Atos Outlines Plans to Get Acquired, and a Path Forward

May 21, 2024

Atos – via its subsidiary Eviden – is the second major supercomputer maker outside of HPE, while others have largely dropped out. The lack of integrators and Atos' financial turmoil have the HPC market worried. If Atos goes under, HPE will be the only major option for building large-scale systems. Read more…

Everyone Except Nvidia Forms Ultra Accelerator Link (UALink) Consortium

May 30, 2024

Consider the GPU. An island of SIMD greatness that makes light work of matrix math. Originally designed to rapidly paint dots on a computer monitor, it was then Read more…

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…


Nvidia Economics: Make $5-$7 for Every $1 Spent on GPUs

June 30, 2024

Nvidia is saying that companies could make $5 to $7 for every $1 invested in GPUs over a four-year period. Customers are investing billions in new Nvidia hardwa Read more…

Nvidia Shipped 3.76 Million Data-center GPUs in 2023, According to Study

June 10, 2024

Nvidia had an explosive 2023 in data-center GPU shipments, which totaled roughly 3.76 million units, according to a study conducted by semiconductor analyst fir Read more…

AMD Clears Up Messy GPU Roadmap, Upgrades Chips Annually

June 3, 2024

In the world of AI, there's a desperate search for an alternative to Nvidia's GPUs, and AMD is stepping up to the plate. AMD detailed its updated GPU roadmap, w Read more…

Some Reasons Why Aurora Didn’t Take First Place in the Top500 List

May 15, 2024

The makers of the Aurora supercomputer, which is housed at the Argonne National Laboratory, gave some reasons why the system didn't make the top spot on the Top Read more…

Intel’s Next-gen Falcon Shores Coming Out in Late 2025 

April 30, 2024

It's a long wait for customers hanging on for Intel's next-generation GPU, Falcon Shores, which will be released in late 2025.  "Then we have a rich, a very Read more…

Leading Solution Providers


Google Announces Sixth-generation AI Chip, a TPU Called Trillium

May 17, 2024

On Tuesday May 14th, Google announced its sixth-generation TPU (tensor processing unit) called Trillium.  The chip, essentially a TPU v6, is the company's l Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

IonQ Plots Path to Commercial (Quantum) Advantage

July 2, 2024

IonQ, the trapped ion quantum computing specialist, delivered a progress report last week firming up 2024/25 product goals and reviewing its technology roadmap. Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

The NASA Black Hole Plunge

May 7, 2024

We have all thought about it. No one has done it, but now, thanks to HPC, we see what it looks like. Hold on to your feet because NASA has released videos of wh Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing po Read more…

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion Read more…

  • arrow
  • Click Here for More Headlines
  • arrow