IBM, Tokyo Electron Announce 3D Chip Stacking Breakthrough

By Oliver Peckham

July 7, 2022

The battle against the slowing of Moore’s law continues. The latest front: 3D chip stacking, which has seen high-profile efforts from several companies as they seek to turn “transistors per unit area” into “transistors per unit volume.” Now, IBM and Japanese semiconductor company Tokyo Electron are announcing a new breakthrough in 3D chip stacking that removes the need for a glass wafer base, streamlining the process.

The stacked silicon wafers that comprise a 3D-stacked chip are, during production, mounted on a carrier wafer. Those wafers can also be made of silicon, but separating the silicon carrier wafer from the silicon wafer for the chip is tricky, and the mechanical force that is typically used to perform the separation can damage the remaining wafers. So, instead, carrier wafers are typically glass wafers removed with ultraviolet lasers.

IBM and Tokyo Electron, however, have found a way to enable silicon carrier wafers for 3D chipmaking without the current drawbacks. Their new method uses an infrared laser to debond the silicon carrier wafer from the other silicon wafers. The two companies say that this has a number of benefits: first and foremost, it removes the need for glass in the production process, but it also, they say, reduces compatibility issues, reduces defects and process issues and enables testing of thinner wafers and other new technologies. This process was demonstrated using a new 300mm module, which the companies say is the first 3D stacked silicon chip wafer at the 300mm level.

The two companies—partners for more than 20 years—have been working on this laser debonding technology for four years, including the construction of a beta system in Albany, New York—specifically, at the Albany Nanotech Complex, a semiconductor R&D hub. Next, they plan to further beta test the laser debonding tech as they approach implementation into an actual manufacturing line.

IBM sees 3D chipmaking as a growth area, citing an expected 10.1 percent compound annual growth in the 2.5D/3D chip packaging segment through 2029 (per a report from Global Industry Analysts). Indeed, companies like AMD and Graphcore have been investing heavily in stacked chip technologies over the last year. IBM is hoping that its investments in 3D stacked chip technology can help streamline the production process and offer a silver lining to the global chip shortage that is currently plaguing producers and consumers alike.

“While chip stacking is not new, and has been used by many chip manufacturers, the process IBM and Tokyo Electron have created should make it more efficient to produce stacked chips at scale, and as a result create more complex designs at a lower defect rate,” commented Jack Gold, president and principal analyst at J.Gold Associates. “Of course, this is still at the prototype stage so it needs to be fully implemented in a fab production line. But if it scales out it could make high performance stacked chips more capable and enable more creative designs produced as building blocks connected together rather than flat monolithic designs, which given today’s chip complexity, are really stretching the boundaries of fab processes.”

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