Tachyum CEO Talks up the Present and Future of Its Universal Chip

By Agam Shah

July 18, 2022

Chip company Tachyum has designed what it calls a “universal processor,” which has been under development since the company was founded in 2016.

The chip, called Prodigy, has been touted as a single chip with combined functionality of a CPU, GPU and TPU. The company has conducted simulated benchmarks where it assessed the chip’s performance to be superior than the fastest Intel Xeon CPU and Nvidia’s datacenter GPU for high-performance computing applications.

The numbers raised eyebrows and skeptics have questioned those claims, but the company’s CEO Radoslav Danilak isn’t perturbed. In an interview with HPCwire, he acknowledged delays and hopes to get working chips to partners by the end of the year, with customers getting it sometime next year.

The Microprocessor Report, a well-known semiconductor publication, said the chip has a frequency of up to 5.7GHz, which is faster than CPU and GPU cores. The chip has a VLIW-style instruction set, and a TDP of 950 watts. The chip is being made on TSMC’s 5nm process.

Tachyum, which is based in Slovakia, has raised $42 million in funding so far from investors. Danilak has an extensive chip development background, and worked as an architect for Nvidia’s Fermi architecture. He also founded Skyera, which was acquired by Western Digital, and Sandforce, which was acquired by LSI. Tachyum’s advisors include Fred Weber, formerly CTO at AMD, and Steve Furber, who designed the BBC Micro and the first Arm 32-bit RISC CPU.

In an interview, Danilak addressed the upcoming Prodigy chip, release dates, and the company’s plans around systems. Here’s the lightly-edited transcript.

HPCwire: You’ve called Tachyum a universal processor that can be a CPU, GPU and TPU. Is it similar to an x86 chip in that it can boot to an operating system? Or is it an accelerator, like a GPU or Google’s TPU?

Chi To, Director of Solutions Engineering, Tachyum, with Prodigy Universal Processor FPGA prototype

Danilak: First of all, it’s a standalone microprocessor. It’s fundamentally a CPU, which improves the performance of vector processing for high-performance computing. The vector unit was extended for matrix operations and AI data types to get high performance in AI.

It boots and runs Linux, it runs FreeBSD, and other applications. It runs standard compilers, like GCC, we will have LLVM and so on. It’s not a GPU, we don’t do any graphics. We do powerful vector processing so it can take on the general-purpose GPU aspect of high-performance computing. It’s a microprocessor where the vector unit can also handle AI, matrixes. It is not TPU, it is not three different chips in one piece of silicon. It is a microprocessor with larger vectors.

HPCwire: To be sure, is it a new chip architecture for CPUs?

Radoslav Danilak

Danilak: It’s a new architecture because it is solving some fundamental problems with other architectures. We have 128 cores. Every core is faster on SPECint than Intel cores. And it’s mesh, and fully coherent. Every core has cache around it.

HPCwire: Tachyum is claiming higher performance in Prodigy over CPUs and GPUs. Some concerns and questions have been raised about the claims. Can you shed some light on the comparisons?

Danilak: Sure. Let me start with this easier part of comparison against CPUs. Let’s compare against AMD CPUs.

AMD, their vector unit is 256-bit vectors. We have kilo-bit vectors, so the unit itself is able to do four times more work. Second, AMD has 64 cores, we have 128 cores, so we have twice as many cores. Third thing, we run at double speed. Another very important aspect is that if you have vector cores and you cannot access unaligned vector in one step, you have to cross the cache line. Intel and AMD execute it at half speed. We don’t have that penalty. So 4x bigger, wider vectors, 2x more cores, 2x speed and 2x more efficiency. Against Intel, there are only twice as wide vectors, but three times more cores because Intel only has 40 cores. Also, double clock speed and double efficiency.

Nvidia is claiming 30 teraflops. However, first thing, GPUs, they don’t run at 5 to 6 GHz, they run generally at 1.3 to 1.5 GHz. If you are running at 1.3 GHz and you have a CPU which runs at 5Ghz, that means for the same performance you need four times less [area], or for the same area, one unit can produce four times more operations. So, the benefit versus CPUs are coming pretty much from clock speeds.

HPCwire: Nvidia has specialized cores and software libraries in CUDA to max out the performance of AI only on their GPUs, particularly on frameworks such as PyTorch and TensorFlow. That’s where apples-to-apples comparisons seem to make sense. Could you talk about the frameworks on your chip?

Danilak: Like TensorFlow or Pytorch, the high-level language is the same. It can run on the GPU or our system. What is happening inside TensorFlow and Python — they work differently for a GPU. They translate to CUDA and they launch a bunch of very small threads. In our case, it translates to CPU code, which basically executes the matrix operations. So that is the key difference. A customer using Pytorch or TensorFlow doesn’t know the difference, They work at a higher level and the rest of everything is hidden from them.

HPCwire: Why make a CPU and not an accelerator?

Danilak: If you look in the cloud microprocessor space, which is a subset of microprocessor space, last year, more than $30 billion of processors had been sold. But Nvidia, in the AI acceleration space, sold less than $3 billion for AI acceleration. They have about 90 percent market share of acceleration. That’s why AI acceleration startups sell systems and services. And that’s the reason we [have] a microprocessor where you also get your high-performance computing.

HPCwire: When you say the chip has native x86, Arm and RISC-V binaries, is there any software emulation layer on top of it?

Danilak: It’s kind of like Rosetta, which Apple has to run x86 on Arm. In our case, our technology is QEMU technology.

We have native Linux, so you can boot from some device, it can be an SSD. You boot and run Linux, and then when you try to start x86 or RISC-V application, the Linux loader is modified to see what is the architecture code. If it discovers that architecture code is not our native code, it transparently launches QEMU – of course QEMU is on the main media from which Linux is booted – that’s how it works transparently. It is a regular application after a Linux boot, it is not firmware.  Both Linux and QEMU are native on our instruction set, but you can run applications from other architectures.

HPCwire: But suppose I have CUDA code, then a chip from Nvidia is better for me. That’s my thought.

Danilak: Why have a GPU and CUDA when you can run the same stuff directly? We support the PCI Express standard and in the second generation we will support PCI coherence. If somebody would have some need to be coherent because of networking or some other application, they will be able to also do it.

HPCwire: What about software overhead typically associated with application performance?

Danilak: First of all, it’s an issue. If you have four times higher throughput in native applications, you will lose about 30 percent – which means if you ran through QEMU, you will be about 3x faster. All our customers over time want to go native. Temporarily, the most critical applications like databases and web servers are already native. Other applications we can run on x86 variables, so the [overall chip performance including emulation] loss is more like 10 percent. Then in over a year or so everybody wants to get their application native to get the remaining benefits of performance.

HPCwire: In the larger picture of chips, clear lines are being drawn between logical and deterministic computing. What is your chip designed to address?

Danilak: Basically, you have what is called the integer core where you do control applications and web servers and so on. And for the floating point or AI application, there’s the vector unit. The structure is … like a general-purpose processor that basically has the execution you need, schedulers and reordering. And then the vector processor is conventional vector units, like AVX-512 in Intel, it’s just wider. You can process more data. The integer is about being fast – it has to be faster per clock – and vector is about not only being fast but wider to do more operations.

HPCwire: How do you measure vector performance – you mention it is twice as wide compared to Intel. Is that the throughput or something else?

Danilak: Yes, it is throughput. Because you do twice as much work, you have twice as much data, and you do the processing of data in one step. So if you have twice as wide vectors, you process twice as much data, which means you do twice as many operations.

HPCwire: Is it like you have something similar to an AVX-1024? Is that the right way to measure it?

Danilak: Intel’s AVX-512 is 512 bits. And you can issue two instructions. In our case, you can issue two instructions, but 1,024 bits. So you can claim that two 512-bit operations as one 1,024 bit operation. You are right, conceptually. But if you want to look at it that way, we can say that two of our 1,024 bit operations can be viewed as one 2,048-bit operation. So, either way, it’s twice as much compared to Intel or 4x compared to AMD.

HPCwire: What is the difference between the Prodigy CPU chip that can be booted and the version on the FPGA?

Danilak: Before you send a chip to production, you basically want to run enough software and test it. What do people do? They run at lower speed, they burn it to an FPGA so you can run the software and debug and see the performance. That’s what we do. The FPGA is not a product that will be shipped to customers. It is a development platform for some customers.

HPCwire: There’s been this big change in chip design from one-size-fits-all chips to a modular approach with chiplets. If someone just needs the accelerator portion of your offering, will your chip play with others?

Danilak: Our first chip is conventional, like every other chip. Chiplets – you cannot buy them and build the products yet. In our second generation, we are looking to basically split one die into maybe two smaller [dies]. It’s not necessarily a chiplet… multi-die is probably a better word.

HPCwire: When is the chip going to come out? You’re taking preorders for the evaluation platform, but there have been delays in the past.

Danilak: Nuvia started roughly the same time, they had like almost 10 times more money, they spent almost half a billion, their chip will be available next year. We are not slower than them. Then the DDR5 memory, which is available this year, supposedly should have shipped a year earlier. During COVID, with DDR5, the whole industry was delayed – startups like Nuvia and so on got delayed. We had a similar delay as the whole industry. It was no different than others, including memory vendors in our space.

HPCwire: You started taking pre-orders last month for a limited quantity of Tachyum Prodigy Evaluation Platforms. Why even a pre-order?

Danilak: It takes four to six months to order the components, voltage regulators. As a small startup we cannot plug tens of million dollars for that. We need to know how many [systems] you need to build and how many people are really interested to pay. Based on that we start purchasing material. We told our partners they had to purchase systems and they are okay with that.

HPCwire: The messaging of your chip being a universal processor and being faster than x86 and GPUs has raised questions. What feedback are you getting?

Danilak: People who for the first time see it think it will be wonderful. It’s possible. They understand the value, but question if it is possible. The people who understand and study it deeper and understand how it is working are saying ‘it looks like it’s doable.’ They like the concept of universality. Intel is focused on CPUs, Nvidia on GPUs, and they are strong in their space. Our technology is kind of almost in between.

Our customers prefer to use our standalone system. It technically supports the accelerated case, but it will be complicated with x86 and reducing performance. GPUs cannot run Linux, so they are accelerators. In our case, customers want to use our standalone systems.

HPCwire: You could get rid of the skepticism when you put the products into the hands of customers. When will that happen?

Danilak: Typically before you go into production, you go through the sampling. You give your closest partners [chips] to test and sometimes they discover some issues and before production, they do something that is called stepping. We expect the tape-out this year and if everything goes well, we might be able to get samples by the end of December.

HPCwire: Will it be in the customers’ hands at that point or will that take longer?

Danilak: Initially you give only to a few partners. They will test it… then, for general availability you need at least something like 100 to 120 days. So that would be the end of Q1 next year, or early Q2, for general availability. That’s the process in other companies.

HPCwire: How will you sell your chip? Do you build systems or do you sell the chips to system builders?

Danilak: We are building a reference design which we will give to our partners so they can build systems. Initially for a few months, we will build systems so the customer can test it. The moment our partners are able to have their own design and ship systems, we will just be a chip company.

HPCwire: Have customers expressed interest in the system?

Danilak: With many customers we have NDAs, so I cannot really talk much, but a bunch of large partners and customers have been kind and allowed us to have joint memorandum-of-understanding press releases. These customers you can find on our website.

HPCwire: What’s your roadmap look like? You’ve already talked about a second generation.

Danilak: We’ll take the same design, we’ll just focus on reducing power and area, so you’ve got an increased number of cores and more than double performance, and shrinking that to the 3nm process.

HPCwire: Is TSMC your manufacturer with its 5nm process?

Danilak: Yes, TSMC.

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