AMD Previews 400 Gig Adaptive SmartNIC SOC at Hot Chips

By John Russell

August 24, 2022

Fresh from finalizing its acquisitions of FPGA provider Xilinx (Feb. 2022) and DPU provider Pensando (May 2022), AMD previewed what it calls a 400 Gig Adaptive smartNIC SOC yesterday at Hot Chips. It is another contender in the increasingly crowded and blurry smartNIC/DPU space where distinguishing between the two isn’t always easy.

Jaideep Dastidar

The motivation for these device types, presented by Jaideep Dastidar, who joined AMD from Xilinx, closely resembles presentations made by Nvidia, Intel, and others in recent years. Host CPUs are overworked with housekeeping chores (networking, storage, security tasks). This is complicated by increasing performance and bandwidth demands, the disaggregation of resources, and rise of software defined everything.

Dastidar said, “[The] reason for moving towards smartNICs and DPUs [is] it all started with the movement in the industry towards software defined networking, which quickly expanded to software defined storage, and before you knew it, you had software defined everything. Meanwhile, the relentless march of speeds and feeds continue, network bandwidths have rapidly increased 25, 50, 100, 200 gig. And the level of virtualization has also expanded ones where you have VMs and the single digits (VMs) has already moved up to the 10s and with containerization, you’re dealing with 1000s of virtual entities.

“All of this resulted in a situation where you had an overburdened CPU. So where the CPU instead of running multi-tenant applications, was absorbed by running datacenter infrastructure. So, to the rescue came smartNICs and DPUs, because they help offload those workloads from the host CPU, and then the host CPU can go back to focusing on multi-tenant cloud applications.”

This is, by now, a familiar message. It will be interesting to watch how the market evolves. AMD is promoting its smartNIC as a flexible efficient SOC that leverages fixed logic ASIC technology where appropriate, more flexible programmable logic (FPGA) where appropriate, and embedded processor cores. AMD, of course, is positioning itself as a strong provider of all three types of technology (ASIC, FPGA, and CPU/core).

Like others, AMD is also baking advanced security management into its system. Use cases are potentially quite varied spanning network management, storage management, and security. Support of CXL 2.0 was notable.

“CXL is definitely a nascent technology. In type two devices, you can cache host memory, as well as have device-attached memory that is accelerated. Right now, with the programmable logic, we just we wanted to offer the flexibility so that you can either attach the smartNIC as a traditional PCIe endpoint, but you can also explore use cases. From a CXL perspective, you kind of need a whole bunch of ecosystem support and such so we’re just creating the capability – creating the foundational technology – so that people can go explore the different use cases that may run better as a type two CXL device,” said Dastidar.

Using the slide above as a map, Dastidar provided a tour of AMD design thinking: “We decided we’re going to take the traditional hardware-software co-design paradigm and extend it to hardware-software-programmable logic co-design. What you see in the figure (slide above) on the right, at the top, we apply ASIC logic where it does best: crypto offload, DMA offload, and even full network data plane offload. Then as you go in the clockwise direction, we’ve added ASIC-to-programmable logic adapters, where you start wanting to layer in customizations such as custom header extensions. Continuing in the clockwise direction, you can also completely hot-add or remove new accelerator functions in the programmable logic. Then if you want to tilt the scales all the way, we wanted the ability to have the SOC do full custom data plane offload as well.

“Continuing in the clockwise direction. When you have programmable logic agents that need to interact with the embedded processing subsystem, we have software-to-programmable logic adapter interfaces, such that you can create coherent IO agents interacting with the embedded processor subsystem. Now the embedded processing subsystem has been dimensioned to run the network control plane. If you notice, this is the first time we mentioned the control plane. Meanwhile, the data plane is being completely executed, either in the ASIC logic or the programmable logic or a combination of the two,” he said.

Of the telemetry functionality, Dastidar said that while the telemetry data is SOC-wide, the embedded processing subsystem is the “best place to gather all that telemetry data, synthesize it, and then upload it to the cloud management plane should they choose to.”

The SOC will be manufactured using TSMC’s 7nm process and be composed of functional blocks. While Dastidar presented a fair amount of material on functionality and supported features, he said little about what the needed programming tools would be.

As shown in the slide above AMD has mapped those design ideas into specific subsystems within the adaptive SOC. The host subsystem contains host connectivity and host domain acceleration. The network subsystem that contains the network connectivity and the network domain acceleration. The processing subsystem contains all the embedded processing cores.

Dastidar said, “While it’s shown here visually, I want you to think about the programmable logic element and the memory subsystem as chip-pervasive resources with chip-pervasive connectivity and access. That connectivity is further enhanced by the programmable network on chip [which] allows for subsystem-to-subsystem data movement, and any of the subsystems can access a common memory location should they choose to in terms of the architecture.”

Dastidar also walked through each subsystem. Here’s a snippet of his description of the host subsystem.

“The host connectivity can be a single host PCIe Gen 5 x16 connection to the smartNIC. Alternatively, it can go all the way up to a quad host 4x Gen five x4 connection to the smartNIC. In addition, the controller supports CXL 2.0 and they can support type one, type two, or type three CXL devices. Now as I mentioned earlier, the PCIe controllers have been upgraded to the latest in PCIe ECN security standards. For example, PCIe CMA (component measurement and authentication), PCIe DOE (device object exchange), PCIe IDE (integrity and data encryption) and the controllers also support TDISP, which allows trusted VMs to communicate in a confidential compute fashion with the endpoint,” said Dastidar.

“The block in the middle is the composable DMA engine. This is a layered data mover. While it can continue to do the traditional offload of host-to-card [and] card-to-host data movement, it also can facilitate subsystem-to-subsystem data movement, and for the host-to-card data it can steer the data to specific subsystems, be it the networking subsystem, the programmable logic, or the processing subsystem.”

Slides showing the other three subsystems are included at the end of the article.

There’s a lot to digest and unpack still. Dastidar did not say when the product might be launched. It’s worth noting that the new smartNIC is based on Xilinx’s Versal ACAP (adaptive compute acceleration platform) smartNIC architecture. During Q&A Dastidar’s answer to a question about distinguishing AMD’s new smartNIC from Pensando DPUs and Xilinx’s Versal smartNIC was a little hazy.

“[We find] the combination of Xilinx smartNIC technology and Pensando DPU technology complement each other really well. Different customers in the datacenter have different models of engagement. This broad portfolio now that AMD offers gives the customer the choice to engage in any of those models. You know the deployments in the datacenter are not homogenous. There are cases where a customer may find the adaptive SOC-based smartNIC to be particularly attractive for a certain node in the datacenter and the DPU-based smartNIC from Pensando also to be very attractive. One common element we’ve noticed is this very strong focus on customer ease-of-use. From a cultural perspective, there’s a very close match, both from an adaptive SOC in terms of how the customers will interact with this SOC as well as Pensando. There’s a lot of investment, a lot of effort to make sure the customer ease of use is top priority.”

These are still early days in AMD’s incorporation of Xilinx and Pensando and it is perhaps not surprising that product line integration and harmonization are not yet settled. The smartNIC/DPU market is quickly becoming more crowded and will be interesting to watch.

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