Intel is opening up its fabs for academic institutions so researchers can get their hands on physical versions of its chips, with the end goal of boosting semiconductor research and development.

The effort, called the university shuttle program, will provide public and educational institutions access to “modern technology for their classes, training and talent development,” said Intel CEO Pat Gelsinger, during a keynote at last week’s Innovation Summit.

Large chip designers like Apple and Nvidia with deep pockets were able to pay their way to dominate manufacturing lines at the fabs of Taiwan Semiconductor Manufacturing Co. and Globalfoundries during chip shortages. Smaller chip companies like AI chipmakers with limited budgets were squeezed and unable to secure manufacturing during the shortages.

Intel’s program aims to alleviate the problem, and will combine a bunch of small orders that can be manufactured as a single batch in the company’s fabs. That could include prototype chips ordered by university professors and students designed using EDA tools.

“We want to build that talent pipeline for the future. And we’re going to work with these institutions to radically increase the semiconductor talent flow of tomorrow,” Gelsinger said during his keynote.

Intel’s expansion of the university shuttle program comes a few weeks after the U.S. government outlined its plans for the U.S. CHIPS and Science Act. One focus is on strengthening the workforce through training and university programs in chip manufacturing and design.

Intel has been a steward of research and development in academia for decades. But now there’s a global battle to attract the best semiconductor talent, with Europe also implementing incentives to build a stronger workforce.

Other shuttle programs already exist, notably a Google effort to open-source chip design and manufacturing. Google’s program, called OpenMPW, provides free chip design and manufacturing tools with the goal to boost research and talent. Many of the chip designs emerging from the effort are based on the RISC-V architecture, which is an open-source instruction set architecture.

Google has partnered with chip manufacturers SkyWater and Globalfoundries to manufacture the chips, which can be made via EDA tools offered by Efabless. The effort is also funded by the U.S. Department of Defense and National Institute of Standards and Technology.

Intel was light on details on how the company will operate and fund the program. The program is part of the company’s $1 billion effort to fund startups and researchers to promote chip design. Intel is also supporting the Arm, RISC-V and x86 architectures in its manufacturing nodes.

Intel provides a process design kit to optimize chip designs to specific processes. Intel is also opening up its 16nm “Intel 16” process to third-parties, and that’s more advanced than the 90nm and 130nm nodes offered in Google’s OpenMPW program. It’s usually significantly cheaper to make chips on the older nodes, and it may be more expensive to make chips on Intel 16.

In a breakout session at Innovation, Intel executives did not comment on the cost associated with academic institutions or researchers to get chips made at Intel foundries, or whether the company would foot the bill.

“We’re trying to encourage all the professors in universities to collaborate together on research but also build the very best IP,” said Bob Brennan, vice president and general manager for Intel Foundry Services Customer Solutions Engineering, in response to a question about the university shuttle program by HPCwire.

Intel is expanding its foundry services with new factories and expansions of existing fabs in the U.S. and Europe. Intel is expected to receive some of the roughly $50 billion in funding that the CHIPS Act opens up to construct its factories. Intel’s university shuttle plan also aligns with the U.S. government’s effort to boost the workforce and talent.