One of the original RISC-V designers this week boldly predicted that the open architecture will surpass rival chip architectures in performance.

“[The] prediction is two or three years we’ll be surpassing your architectures and available performance with designs that are in flight right now,” said Krste Asanović, professor of computer science at the University of California, Berkeley, during a keynote at the Supercomputing 2022 conference.

But participants on the Supercomputing show floor were skeptical about the preparedness of RISC-V for high-performance computing, saying it was nowhere close to ready as a mainstream alternative to x86 or Arm.

Commercial chip companies estimated a realistic timeline of close to five years or even longer before RISC-V made a meaningful dent in the market.

Nonetheless, there was a lot of momentum behind RISC-V on the show floor, and participants agreed that the architecture couldn’t be ignored and would ultimately make its way to mainstream HPC.

RISC is an open chip architecture, which is free to license. Customers can add their own extensions and customize the chip for a number of applications that include artificial intelligence, mobile and industrial applications.

RISC-V is not yet a viable go-to market option for high-performance computing, SiPearl CEO Philippe Notton, told HPCwire.

The chipmaker has developed an Arm-based CPU called Rhea, which will go into future exascale systems in Europe. The chip has 29 RISC-V microcontrollers to support the Arm CPU.

SiPearl was born out of funding from the European Union, which has a long-term goal to develop home-grown processors. The European Processor Initiative, which is also funded by the EU, is focusing on developing chips with RISC-V to break away from the proprietary x86 and Arm technologies.

SiPearl – which was founded in 2019 – had to deliver a high-performance CPU quickly for European consortiums involved in creating exascale supercomputers, and Arm was the only option to develop a customized chip.

RISC-V is still a long way from being commercially ready, Notton said, adding that he is open to designing a chip based on the architecture. Until then, Arm has a more reliable hardware and software ecosystem, and toolset that it can provide to customers.

“It’s tough to say because our own RISC-V chip will need to be serious in HPC,” Notton said.

If RISC-V emerges, Arm will react and do something about it, Notton said.

Intel is working closely with the Barcelona Supercomputing Center to build a RISC-V chip for supercomputing. But RISC-V for HPC is “many years away,” said Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel.

BSC hopes to add a performant RISC-V processor on Europe’s roadmap, and has a rich history of experimenting with new chips. The supercomputing center’s partnership with Intel is more around the incorporating a RISC-V core into chiplets, which is a new type of chip design in which multiple processor modules can be crammed in a single chip package.

Intel’s manufacturing future revolves around chiplets, which will add design flexibility with the ability to put CPUs, GPUs, I/O, memory types, power management and other circuits in a chip package. Intel is developing a server chip called Falcon Shores for the 2025 timeframe, which will integrate Intel’s GPU and x86 CPU design in a chiplet form.

The BSC partnership is looking at future variants beyond Falcon Shores that allow the integration of RISC-V as a primary CPU alternative to x86, McVeigh said.

There’s a lot more work to be done to bring RISC-V to HPC beyond designing a chip, McVeigh said.

“We’ll see. It’s a long process to code porting, performance, all those things, but we think there is a potential future,” McVeigh said.

The most enthusiastic RISC-V backers were academic researchers designing indigenous chips for Europe.

The Jülich Supercomputing Centre in Germany, which hosts some of the world’s fastest supercomputers, is interested in many architectures, including RISC-V, said Estela Suarez, head of RG next-generation architectures and prototypes at Forschungszentrum Jülich

“We are a little bit on the higher layer of software development. We ensure that the hardware stack is supported,” Suarez said.

RISC-V is designed as a modular instruction set with a very small base of less than 50 instructions. Custom cores that can be tacked on to the base ISA like Lego blocks. The expansiveness of RISC-V is seen as a strength compared to rivals relying on integration.

The weaponization of chips by countries and regions has ramped up efforts to create indigenous chips in Europe and China based on RISC-V. The U.S. has banned the export of advanced CPUs and GPUs to China. The U.S has also banned all semiconductor exports to Russia, where companies like Yadro also have RISC-V designs in the works.

The European Processor Initiative expects native RISC-V accelerators for applications like AI to come much quicker than general-purpose CPUs.

EPI’s high-performance accelerator called EPAC, which is based on RISC-V architecture, has Avispado vector processing units developed by Semidynamics, and a RISC-V CPU developed by Kalray, which is based in France. It also has a tensor accelerator, and an on-board FPGA for reconfigurable logic.

The first EPAC version was taped out last month, and a followup, EPAC-2 is on the roadmap for 2024. The EPAC-2, along with the Rhea 2 chip, is targeted for deployment in European exascale supercomputers starting in 2024, according to EPI’s roadmap.

“What is really important is that we have European support for building the whole chain of knowledge that you need to make good chips. It is not enough to have somebody with a good architectural idea on a blackboard unit,” said Filippo Mantovani, senior researcher at Barcelona Supercomputing Center.

The bigger point is to develop European expertise and a thriving semiconductor ecosystem in the region, which will benefit chip companies in the region, said Mantovani, who also leads the accelerator development at EPI.

BSC and other universities were also involved in the development of Monte Cimone, a high-performance computer based on the RISC-V architecture.

The Monte Cimone cluster includes eight computing nodes in four blades. Each node has SiFive’s U740 chip, which has four 64-bit U74 cores with frequencies of up to 1.2 GHz. The systems – which were SiFive HiFive Unmatched boards – had 16GB DDR4 memory, 1TB of NVMe storage, and PCIe expansion cards, according to a research paper talking about the system.

The system was created to test applications and their performance, much like the Mont Blanc system from more than a decade ago, which was used to test Arm processors in HPC environments. Arm processors are now in the world’s second-fastest supercomputer, called Fugaku, which is deployed at the Riken Center for Computational Science in Japan.

The Monte Cimone study, led by the Italian supercomputing center CINECA, noted that while RISC-V deployments are growing and the software stack is maturing quickly, it is still “apparent that the performance and number of cores in the SoC is not sufficient to achieve performance comparable to mature Arm and x86 cores.”

RISC-V International, which manages the development of the ISA, has the backing of some of the biggest chipmakers. The ISA is also being used in a TPU chip being developed by Google, and Intel and SiFive have shown a computing board called Horse Creek, which was made using the Intel 4 process and supports the latest DDR5 memory and PCIe 5.0 interface.

Asanović made a case of historical computing trends being in the favor of RISC-V. Instruction sets widely used in high-performance computing at times, including DEC’s Alpha, Intel’s Itanium and Oracle’s SPARC, have vanished.

Proprietary chip designs like x86 and Arm could face challenges as more chips are customized. The x86 architecture dominated the “board” era which focused on integration, and Arm dominated the mobile era with integrated modems and GPUs. But as chip customization grows, companies are against betting their future on a proprietary design, and RISC-V makes more economic sense and can be extended to more computing capabilities.

RISC-V International has a special interest group push for HPC, and has projects underway to add HPC capabilities to RISC-V. There are also many people contributing to the ISA from academia and the industry, making it a community effort.

“We even have a 128-bit address base version in draft form because we’re going to need that by the end of the decade,” Asanović said.

For now, HPC is just not a big enough market to justify custom silicon, so the chiplet model will help design chips with accelerators at a reasonable cost.

“RISC-V… is inevitable,” Asanović said, adding “think about Ethernet. Think about Linux. This is what is happening with RISC-V.”