PCIe Market to Hit $50B; PCIe 7.0 v 0.3 Now Available

By John Russell

June 13, 2023

Steady technical progress and continued market traction were key points of emphasis coming from the PCI-SIG Developers Conference held this week in Santa Clara. According to a new ABI Research report, the PCIe market will grow 14 percent (CAGR) from 2022-2027 and hit $50 billion worldwide. High growth verticals cited including datacenters, edge computing, telcos, AI, automotive, mobile devices and wearables.

On the technology front, PCI-SIG (Peripheral Component Interconnect Special Interest Group) released PCIe 7.0 v 0.3., to PCI-SIG members just before the conference. “Version 0.3 of the specification indicates that the first review draft of the specification is complete and has received work group approval,” said Al Yanes, CI-SIG president and chairperson. “This is an important milestone for PCI-SIG, demonstrating we are on plan for a full specification release in 2025.”

PCI-SIG says the new PCIe 7.0 spec targets emerging applications such as 800G Ethernet, AI/ML, cloud and quantum computing, as well as data-intensive markets like hyperscale datacenters, HPC, edge, and military/aerospace.

PCIe[i] and its forerunners have been around for a long time (1992). Today PCI-SIG, the standards organization, has nearly 1000 members. It’s worth noting that while interconnect technology is a very active development area – particularly for onchip/onpackage and inside heterogeneous computer systems – PCIe has largely held onto its preeminence as the ubiquitous card/peripheral to motherboard standard. There’s even been work using PCIe as a fabric for composable computing ideas.

In a pre-briefing with the media, Yanes highlighted PCIe’s wide range of features and performance levels available. He also reviewed the status of work on PCIe 6 and, PCIe 5 (cabling) in the press briefing. Shown below are slides summarizing those efforts.

The new ABI Research report paints a rosy picture for PCIe. Yanes reviewed some of the key targets. PCI-SIG is making the full report available to its members.

“I’ll just touch on some of the highlights,” said Yanes. “One is the automotive space. [ABI] sees an increased adoption in the automotive space related to crucial electronic communication and self-driving. They see L0p[ii], which is our new low power state, as an enabler for the low power solutions like mobile AI. It’s been in the news recently [that] AI needs a lot of bandwidth. PCI Express has always traditionally had a tremendous amount of bandwidth. This [report] is showing that for the next many years, PCI Express technology is going to be healthy choice for our members.”

Key highlights from the report:

  • Automotive and network edge verticals projecting the highest growth opportunities for PCIe technology, with total addressable market (TAM) and compound annual growth rates (CAGRs) of 53% and 38%, respectively, over the forecast period.
  • The automotive industry can extract significant value from widespread PCIe technology adoption, as it enables the consolidation of Electrical/Electronic (E/E) domains, as well as helping systems overcome safety and efficiency challenges within mission-critical applications for autonomous vehicles.
  • High-performance applications such as datacenters will contribute to sustained long -term demand for new PCIe technology deployment. In addition to performance, other critical drivers of PCIe technology adoption are power efficiency, security and “time-to-value”.
  • The low power feature (L0p) of PCIe 6.0 specification will be a major driver of deployment, as power efficiency becomes a central strategy for adopters with a closer focus on sustainability and lowering operational costs.
  • AI industry adoption will be high, as PCIe technology offers decision makers agility through forwards and backwards compatibility, improving time-to-value and lowering deployment risk.
  • Complex Open Radio Access Network (Open RAN or ORAN) workloads will lead to sustained demand for PCIe technology, as heterogeneous hardware becomes ubiquitous.
  • PCIe technology will perform well in the mobile devices vertical, as the quick pace of market innovation will necessitate a discrete component interconnect.

“PCIe technology demand will be sustained in the long run as applications that require faster speeds, embedded security, and greater power efficiency continue to emerge,” said Reece Hayden, research analyst, ABI Research. “In the near term, this is especially true in the datacenter and AI verticals as PCIe 6.0 specification brings much more effective power-management capabilities.”

[i] PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e,[1] is a high-speed serial computer expansion bus standard, designed to replace the older PCIPCI-X and AGP bus standards. It is the common motherboard interface for personal computers’ graphics cardssound cardshard disk drive host adaptersSSDsWi-Fi and Ethernet hardware connections.[2] PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER),[3] and native hot-swap functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization.

The PCI Express electrical interface is measured by the number of simultaneous lanes.[4] (A lane is a single send/receive line of data. The analogy is a highway with traffic in both directions.) The interface is also used in a variety of other standards — most notably the laptop expansion card interface called ExpressCard. It is also used in the storage interfaces of SATA ExpressU.2 (SFF-8639) and M.2.

Format specifications are maintained and developed by the PCI-SIG (PCI Special Interest Group) — a group of more than 900 companies that also maintains the conventional PCI specifications. https://en.wikipedia.org/wiki/PCI_Express

[ii] “Higher speeds, of course, mean higher power, so PCIe 6.0 introduces a new low-power state of operation called L0p Mode. L0p enables traffic to run on a reduced number of lanes to save power. L0p always maintains at least one active lane to ensure uninterrupted traffic flow,” Semiconductor Engineering, 1/12/23, https://semiengineering.com/pcie-6-0-takes-data-center-performance-to-the-next-level/#:~:text=Higher%20speeds%2C%20of%20course%2C%20mean,to%20ensure%20uninterrupted%20traffic%20flow.

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