It is becoming clearer that China’s plan to cut reliance on Western chip technology revolves around homegrown chips built using the open RISC-V architecture, which is also gaining popularity in the Europe and U.S. 

China has for years has talked about moving its chip strategy in the direction of RISC-V, which is a free-to-license API blueprint to build chips, but no serious action was taken.  

Previous efforts to make sovereign chips around alternative architectures went nowhere. But this year the China government has finally shown seriousness about funding RISC-V initiatives.  

The Chinese government’s sudden interest in RISC-V came overnight, and that was a surprise to academic Yungang Bao, who is the deputy director of information and communications technologies at the Chinese Academy of Sciences (CAS). 

“This year, the Ministry of Science and Technology and the National Science Foundation China are already inviting proposals for RISC-V related research. This is quite a substantial change,” Yungang said during a presentation at the RISC-V Summit held last month in Barcelona. 

In 2012, China’s Ministry of Industry and Information Technology proposed to merge all kinds of chip architecture blueprints being used in the country into a unified design. Those architectures included x86, MIPS, PowerPC, Alpha, and SPARC. 

But it became difficult to reach a consensus on how to merge these instruction-set architectures, Yungang said.  

“RISC-V provides an excellent answer,” Yungang said. 

RISC-V, which is free and open-source, provides a faster and cheaper alternative to design and manufacture chips without relying on Western technologies.  

“Over the past years most RISC-V related work was done, kind of, bottom-up. Today the Minister of Science and Technology is … already paying attention to RISC-V. More universities use RISC-V for teaching, for example. There is already … a textbook based on RISC-V now,” Yungang said. 

In some areas, the U.S. has restricted semiconductors in trade and policy and tightened certain Western AI chip and CPU exports to Chinese organizations. That has forced China to look internally for technologies to develop chips, and RISC-V is emerging as a top option.  

RISC-V research and development started in 2015 mostly at the academic and startup levels but is now rapidly maturing. RISC-V is considered an open technology, much like Linux. The base architecture can be licensed for free and then can be modified by Chinese companies to meet their needs.  The most common commercial alternatives are either to use the widespread x86 architecture, that can only be purchased in manufactured form, or to purchase a licensed design for ARM architectures. 

“Instructions should be free. That’s a totally different mindset.” Yungang said, adding that “many Chinese companies adopt this mindset widely.” 

RISC-V development is managed by RISC-V International, which is a neutral organization and has declared the chip architecture as border-less technology. 

China has had many setbacks in building its homegrown chip ecosystem. The Chinese government has been defrauded to invest billions of dollars in non-existent chip factors, and internally developed chip architectures such as Loongson, which is reportedly a mishmash of RISC-V and MIPS architectures and has not been widely adopted. 

China’s efforts mirror attempts in Europe to create a set of sovereign chips based on the RISC-V and reduce the reliance on companies like Intel and ARM for chips. The EU-funded European Processor Initiative is designing RISC-V chips for AI, supercomputers, automobiles, and other electronics. 

CAS is playing the long game to make RISC-V the default architecture in the China market. The grassroots effort is focused on drawing academic and startup interest in RISC-V. For example, CAS’s goal is to introduce chip design based on RISC-V early in the education process.  

In 2019, the Chinese Academy of Sciences launched a countrywide initiative to promote RISC-V across China. The U.S. has placed the Chinese Academy of Sciences on an entity list due to its affiliation with the Chinese government.  

Chinese organizations also established the China RISC-V Alliance in 2018 to build out a full open-source chip ecosystem by 2030. About 70 Chinese companies are now members of RISC-V International, only behind the EU, which has 87 members, and the U.S., which has 77 members. 

The top 10 RISC-V startups in China have raised close to $1.18 billion in funding from venture capital firms, according to a slide in Yungang’s presentation. 

CAS is working with top Chinese companies, including Alibaba, Tencent, and ZTE, to co-develop XiangShan-v3, which will match the performance of ARM’s Neoverse-N2 server CPU design, which ARM announced in 2021. 

But Yungang acknowledged that there are performance gaps in some of those chips compared to the latest chips released by ARM. The most recent XiangShan-v2, for example, was slightly faster than ARM’s Cortex-A76 smartphone CPU, which was announced in 2018.  But the performance gap is closing as the RISC-V development and verification matures.  

Advanced GPUs and DPUs made using the 7-nm process will also be lined up for use with XiangShan CPU this year, according to a slide during Yungang’s presentation. 

Chinese companies have already released many RISC-V boards. In 2023, Sophon released a 64-core RISC-V CPU, and other companies that include StarFive and Allwinner have RISC-V CPU designs and boards that can be purchased through Chinese retail sites.  

The RISC-V ecosystem in China is built on the open-source ethos, with the community working together to improve designs and software. Yungang’s long-term goal is to create a platform with full chip development platform with open-source chip designs, electronic design automation, and verification tools. 

“The open-source chip ecosystem can lower the barrier of chip development by saving time to market and the cost of IP, EDA tools, and engineers.” Yungang said. 

The platform will also automate chip design, so processors for various applications can be released quickly. 

“Over ninety percent of the code provided by the platform can be easily reused. And then the customized design only needs … less than 10% of code.” Yungang said. 

Another initiative called “One Chip One Student” (OSOC) teaches undergraduate students how to design RISC-V chips. 

In 2019, five undergraduate students in the OSOC program could design a RISC-V processor in four months. The Linux-compatible chip was taped out on the 110-nm process. 

The OSOC has been a considerable success since, with more than 4,000 undergraduate students participating in the program until this year. About 300 universities are participating in the initiative. 

U.S. semiconductor companies are facing an acute shortage of talent in the fast-growing semiconductor sector, due to the high education costs and low interest in engineering courses. 

A lot of RISC-V development in the U.S. is in the hands of the private sector and has faced many setbacks. Most notably, cash-strapped Intel pulled close to $1 billion in funding it had reserved to promote RISC-V development. 

Chinese institutions are currently developing open-source EDA tools to design RISC-V chips. Three tape-outs have been completed on the 110-nm and 28-nm nodes, but it is not viable for commercial use. 

“The performance, the PPA (power-performance-area) is still lower than the commercial EDA tools, but it works. And then next we will let the students use the open EDA tools to build their open-source chips,” Yungang said. 

To some degree the U.S. government restrictions have stifled China’s semiconductor ecosystem by blocking access to some EDA tools for advanced chips. But Yungang repeated that China’s RISC-V efforts are borderless and can be adopted by anyone in the world. 

“Everyone can access the XiangShan project from GitHub. It already has … more than 400 forks,” Yungang said.