A specification that could standardize the development of RISC-V server chips and systems is currently being drafted by RISC-V International, an organization that is handling the development of the instruction set architecture.
The specification establishes standard interfaces for various layers of server computing systems built on RISC-V technology. It could help companies deploy RISC-V servers in cloud computing environments, in which software runs off virtualized CPUs and not directly off hardware CPUs.
To be sure, the server spec is in its early stages. The current iteration includes system management controllers, system-on-chip modules, security layers, boot systems, and virtualization layers.
“The RISC-V server SoC (system on chip) specification defines a standardized set of capabilities that portable system software such as operating systems and hypervisors can rely on being present in a RISC-V server SoC,” RISC-V said in a document defining the specification. A link to the specification is available here.
RISC-V is an instruction-set architecture that is free to license. Anyone can create chips based on the architecture, but companies can also add their proprietary modules and sell those chips. RISC-V is backed by most of the top chipmakers, including Intel, AMD, Apple, Nvidia, and Qualcomm.
The Open Compute Project has also defined similar specs for x86 and ARM servers, which are used as blueprints by server makers to build standardized data-center products.
The RISC-V proposal also provides a base for server systems to support technologies like CXL, which is already backed by x86 and ARM server makers.
The upcoming CXL 3.0 spec provides a high-speed communication link between chips, memory, and storage, and is drawing interest from server hardware makers as it could change the way data centers are built. The spec will cut processing and bandwidth chokepoints by disaggregating compute and storage modules.
The server spec is built on top of technologies in the instruction set architecture such as the newer vector processing specification, which has been ratified in recent years.
Many RISC-V companies are building server chips, with the most notable being Ventana and Esperanto.
The companies have built their own proprietary modules on top of the base instruction set architecture but have said they would standardize to the latest specs ratified by RISC-V International.
Research organizations in the Europe and U.S. are experimenting with RISC-V microservers to develop and test software.
The proposal to create a server spec also reflects the open-source ethos of RISC-V — to jointly develop and improve a product as a community.
“The reason we’re a community at all…is we get to share the burden,” said Mark Himelstein, the chief technology officer at RISC-V International, during a recent presentation at a RISC-V Summit held last month in Barcelona.
The goal is to prevent hardware and software fragmentation in the RISC-V community. RISC-V International wants to avoid the fate of Android, which quickly fragmented as phone developers modified the OS to meet their smartphone needs.
“We share the work of defining the ISA, we share the work of finding the hardware-software interface… and we share the software burden. It means everything from boot code all the way up to applications,” Himelstein said.
RISC-V still is not considered a viable server alternative to x86 or ARM, which dominate the data center market.
“When people say ‘Oh, RISC five is 10 years behind ARM,’ the answer is yes, but it is not going to take 10 years to catch up. It will take a couple of years to catch up,” said Dave Ditzel, CEO of Esperanto Systems, during another presentation at the RISC-V Summit.