Esperanto Merging HPC and ML in Upcoming RISC-V Processor

By Agam Shah

July 31, 2023

Esperanto Technologies has ambitious plans for its next RISC-V processor: to undo the accelerator model and build a chip that has both CPU and GPU capabilities for machine learning and high-performance computing.

“X86 is just too heavyweight to serve as both main CPU. The accelerators and the GPUs are just too hard to program and they can’t really serve as your main CPU, right? RISC-V really has the ability to do both things,” said Dave Ditzel, CEO of Esperanto, which designs RISC-V processors, during a presentation at last month’s RISC-V Summit held in Barcelona, Spain.

Ditzel also shared some details about its next-generation chip that he hopes would serve that purpose: do double-precision computing for HPC, and lower-precision computations for machine learning applications.

The ET-SoC-2 will include new high-performance CPU cores with the RISC-V vector extensions. The RISC-V standards-setting organization, RISC-V International, is in the process of ratifying new vector and floating-point specifications to be included in the base instructions. The full list is available here.

“It’s going to have pretty substantial performance for one low-power chip,” Ditzel said.

RISC-V is an instruction set architecture that can be licensed for free, and server chip makers are now building processors for AI and enterprise applications. Esperanto is currently selling the ET-SoC-1 chip, and will advance those high-performance computing capabilities in the next chip.

Ditzel did not provide benchmarks for ET-SoC-2 but said it could provide in excess of 10 teraflops of double-precision performance in a single chip.

Dave Ditzel, CEO of Esperanto, presented at last month’s RISC-V Summit in Barcelona, Spain. (Click to enlarge).

“This system is meant to put hundreds or 1000s of these chips cooperatively working together in the future,” Ditzel said.

Esperanto’s focus is more on power efficiency than raw performance, which has been Ditzel’s focus for decades. In 1995, he co-founded Transmeta, which had a software-defined chip that emulated x86 processors and was focused on power efficiency.

Ditzel said the current ET-SoC-1 chip provides 32 CPU cores on a single chip at up to 40 watts, depending on the application.

“Within the next five years, a RISC-V-based system will win what’s called the Green500 award,” Ditzel said.

Green500 is a separate ranking system for the most energy-efficient systems of the Top500 supercomputers in the world.

Ditzel said racks of ET-SoC-1 chips can provide petaflops of performance. But RISC-V lacks a coherent software ecosystem, with very limited application and OS support.

RISC-V processors lag x86 and ARM processors in performance, though companies are closing the gap.

“When people say ‘Oh, RISC five is 10 years behind ARM,’ the answer is yeah, but it is not going to take 10 years to catch up. It will take maybe a couple of years to catch up,” Ditzel said.

Esperanto’s competitors include Ventana, which makes the Veyron V1 chip, which is based on a chiplet design. The Veyron chip can scale up to 16 cores and has L1, L2 and L3 cache, and is being offered as a chip or for licensing.

Many European researchers are also testing out RISC-V development boards as microservers for application development and testing.

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