RISC-V Summit: Ghosts of x86 and ARM Linger

By Agam Shah

November 12, 2023

Editor note: See SC23 RISC-V events at the end of the article


At this year’s RISC-V Summit, the unofficial motto was “drain the swamp,” that is, x86 and ARM, with RISC-V being the replacement, regardless of the device or computing environment. 

There were some big-time commitments to the up-and-coming instruction set architecture at the conference, which was held in Santa Clara.

Meta and Qualcomm said RISC-V architecture is central to their chip development plans. Company executives also left the door open to making primary computing chips from the architecture.

RISC-V is still young, years or even decades away from replacing x86 or ARM. But it has many things going for it. 

The architecture is free-to-license, which lowers the barrier to entry and cost. It also has a flexible design to bring more compute to modern workloads.

Commitments by Meta and Qualcomm also highlighted a sobering reality — that companies are willing to kick proprietary technologies to the curb.

“The market is ready and hungry for options. They do not want to be locked into one proprietary roadmap. They want to have options, and that freedom of choice has expanded,” said Calista Redmond, CEO of RISC-V International, in a chat with HPCwire.

RISC-V can be a barebones scheduler or a fully loaded processor, depending on what customers want. It can be adapted to newer computing models around sparse computing, in which data is closer to the processing cores.

Here are some observations from the two-day event, which was in its sixth year.

Government Attention Thrills

RISC-V Summit attendees were thrilled and upset by the U.S. government’s interest in taming the open standard.

On the one hand, RISC-V came out of obscurity and reached the big leagues by attracting government attention. But the idea of Joe Biden’s administration intervening in developing RISC-V standards got a universal thumbs down.

Participation and engagement are already in motion, and the vibe on the show floor was about sharing ideas and teaming up to improve the RISC-V architecture.

RISC-V is following the footsteps of global standards like Ethernet, USB, and HTTPS, which spurred technological innovations. Short-circuiting RISC-V development could be disastrous and shut down choice and innovation, Redmond said. 

“Proprietary models are a larger trap for geopolitical concerns than open architectures. And I do not think that is something that is truly realized in some of the rhetoric that you’re hearing,” Redmond said.

The Elephant in the Room

The U.S. government’s prying eyes on RISC-V did not stop Chinese company Alibaba from attending the Summit and showing off its wares based on the instruction set architecture. 

In fact, on U.S. soil, Alibaba did one better — the company announced a 3,072-core RISC-V server made using an indigenous Chinese chip. The server has 48 nodes of 64-bit Sophon SG2042 chips and has been deployed at China’s Shandong University.

Alibaba claimed the server was the first commercial deployment of a RISC-V server. There are no known RISC-V server deployments in U.S. cloud services.

At first glance, China is way ahead of the U.S. in the RISC-V race.

China has a cohesive plan to develop indigenous chips based on RISC-V. The government is funding university students and startups to develop chips while the U.S. fumbles and bumbles around how to handle RISC-V.

Concerns about restricting U.S. companies from cooperating with China on RISC-V were not mentioned in keynotes. Instead, speakers talked about the borderless nature of the RISC-V architectures, with almost equal participation from all regions.

The RISC-V Shipment Numbers

Current estimates suggest there are about 10 billion RISC-V cores in the market. A study from SHD Group suggests about 18 billion RISC-V chips will ship by 2030.

Of the 18 billion, microcontrollers top the charts, totaling a bit over 6.5 billion, followed by AI accelerators at 4 billion, network chips at 2 billion, security chips at a bit over 1.1 billion, and general-purpose CPUs at around 900 million. 

Qualcomm, to date, has shipped over 1 billion devices integrated with RISC-V cores. The company first used RISC-V controllers in the Snapdragon 865 chip in 2019 and will expand the instruction set architecture across all product lines.

The SHD Group study was funded by RISC-V companies, so it could be taken with a pinch of salt. But it is the only estimate that quantifies what RISC-V shipments could look like in the future and was conducted by a well-known researcher, that quantifies what RISC-V shipments could be in the future, and was done by a well-known researcher Rich Wawrzyniak.

RISC-V Gobbling Up Other RISCs

RISC-V is the overlord of other RISC designs and forgotten architectures that got lost along the way.

For one, RISC-V this week consumed the ARC architecture, a RISC-based design that can be tracked to decades ago when it was introduced in the SuperFX chip used in the Super Nintendo system.

Synopsys is behind the ARC-V processor, which has now transitioned to RISC-V architecture, and older versions of ARC still support the older architecture. MIPS previously transitioned fully over to RISC-V after abandoning its old architecture.

The convergence of other RISC architectures into RISC-V is all about strength in numbers, Redmond said. 

“Your secret sauce is your implementation and the ability to accelerate the on-ramp of the development community to bring their workloads and applications onto that,” Redmond said.

Security Concerns

Security still is not a first-class citizen in RISC-V designs. Companies insist that their RISC-V chips have secure layers, cryptographic extensions, and more, but it is still the bare minimum.

RISC-V chips are still not ready for applications like confidential computing, in which secure enclaves protect code or applications and are only accessible to authorized entities.

The idea of secure-by-design is trickling into chip developers. With TDX extensions, Intel and AMD, with its SEV-SNP feature, have strong security built into CPUs. Intel’s new APX features also reduce branch prediction, which lowers the attack surface for hackers.

A few vendors focused on security at the RISC-V Summit were on the show floor. Emproof, which is based in Germany, has a security layer that sits after the compiler and can obfuscate and protect binary code from reverse engineering. The company received interest from RISC-V companies looking to protect on-chip features. 

LowRISC, based in Cambridge, UK, has developed a root-of-trust based on OpenTitan, which protects chips from firmware and other attacks on silicon. OpenTitan is an open-source version of the Titan silicon root-of-trust, which Google uses to secure its devices.

Ventana Microsystems Veyron 1 RISC-V processor running at 3.6GHz in 5nm

The Winner

One of the biggest winners was Ventana Microsystems, which announced a 192-core RISC-V CPU core called Veyron V2. The chip pushes the limits of what can be done with RISC-V processors and matches x86 and ARM with the latest interconnects, memory technologies, and chiplet implementations.

The new chip will be 40% faster than the Veyron V1, which was announced a year ago. It also supports the upcoming UCIe interconnect, which is also supported by other major x86 and ARM chipmakers. 

It supports the latest vector extensions ratified recently by RISC-V International, which were not in V1. The V2 has many more enhancements regarding the microarchitecture and the pipeline.

“Basically, we achieved parity with ARM or x86 at a system IP level,” Balaji Bakhta, CEO of Ventana Micro Systems, told HPCwire.  

The Veyron V2 will be made using the 4-nanometer process, which is an advance from the 5-nanometer process for V1. 

Bakhta said high-performance computing companies were interested in the chip. The systems will reach customers next year, Bakhta said.

RISC-V at SC23

There are several RISC-V events at SC23. Consult the show schedule for more information,

The Second International Workshop on RISC-V for HPC workshop will run on the afternoon of Monday, November 13, between 2 pm and 5:30 pm. 

Workshop: Challenges and Opportunities in the Co-Design of Convolutions and RISC-V Vector Processors, Monday, November 13 from 5:10 pm – 5:30 pm MST, Location: 507

Workshop: An Empirical Comparison of the RISC-V and AArch64 Instruction Sets, Wednesday, November 15 from 12:15 pm – 1:15 pm MST, Location: 403-404

Birds of a Feather: HPC Next: The RISC-V Ecosystem Tuesday, November 14 from 5:15 pm – 6:45 pm MST Location 405-406-407

Birds of a Feather: European RISC-V HPC and AI Pre-Exascale Accelerators, Wednesday, November 15 from 12:15 pm – 1:15 pm MST Location 403-404

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