In a few years, servers may not look the same as memory, storage, and accelerators move to separate enclosures. An interconnect called CXL is making that possible.

An upgraded specification of the technology, version 3.1, was announced this week. The incremental update provides a faster, more secure computing environment and a more robust technology base to convert a data center into a giant server.

The new specification will support DDR6 memory, which is still under development. JEDEC, the standards-setting organization for DDR, has not talked extensively about DDR6.

Intel and AMD server chips today support DDR5 and have not guided chipset support for DDR6. A majority of hardware and cloud providers support CXL.

The CXL 3.1 is an incremental improvement from CXL 3.0, which was introduced over a year ago. The CXL protocol is a communication link between chips, memory, and storage in systems.

The CXL 3.0 spec is based on PCIe 6.0 and has a data transfer speed of up to 64 gigatransfers per second. It is two times faster than its predecessor, CXL 2.0, which is based on PCIe 5.0, and is making its way to server systems.

CXL has become an important part of chipsets as technologies like AI become pervasive. Machine learning applications need a lot of memory and bandwidth. CXL allows the pooling of storage and memory across servers.

The CXL 3.1 protocol can open more peer-to-peer communications to disaggregate memory and storage into separate boxes. Disaggregation via traditional networking and interconnect technologies has been discussed for a decade, but CXL provides the extensibility needed to make a wide range of computing resources available.

For one, CXL 3.1 spec provides an opening to support new types of memory and can also reroute data more efficiently to memory and accelerators.

An important advancement involves pooling memory resources on a fabric together under one global address. That feature, called Global Integrated Memory, is important in establishing faster connectivity between memory and other resources.

Accelerators will also be able to communicate directly with memory resources. New features for port-based routing facilitate faster access to memory resources.

CXL 3.1 also provides the hooks for data execution in a protected environment. This technology is being introduced to support confidential computing, which has already been introduced in Intel’s Sapphire Rapids with TDX instructions and in AMD’s chips as the SNP-SEV feature.

The new specification defines a secure protocol that expands the secure environment as data moves between memory, processors, and storage.

The protocol will detect environments where connections need to be authenticated to open hardware vaults to access code or information. The information may be on processors, memory, or storage. Intel, Microsoft, and other companies have different types of attestation methods to verify connections trying to access data in secure environments.