The National Institute of Standards and Technology is awarding $300 million for chip manufacturing research and development, and on Thursday, it shared how it will divide up the funding.
“CHIPS R&D anticipates making available up to approximately $300,000,000 for multiple awards in amounts up to approximately $100,000,000 per award,” the agency said in a recent notice on the US government’s Federal Register, which is an overarching document that also announces rules, regulations, and banned entities.
The funding is provided as part of the US CHIPS and Science Act passed in 2022. The bill provides $52 billion in incentives and funding, with $39 billion in incentives going to companies looking to modernize or expand chip manufacturing facilities.
A good chunk of the remaining funding, about $11 billion, will go to chip research and development. The US government previously assigned $200 million of that funding to materials and substrates R&D, but that amount has gone up to $300 million, according to the government notice.
The CHIPS Act specifically funds NIST’s National Advanced Packaging Manufacturing Program (NAPMP), which aims to create robust domestic advanced packaging capacity to boost the US supply chain.
Intel and TSMC have unique packaging technologies that are critical in putting together chips used in devices. The companies have progressed from 2D to 2.5D packaging and, now, 3D stacking. Advanced packaging can improve the performance and power efficiency of the chips.
The NIST wants to fund forward-looking materials and substrates and will not entertain proposals on older circuit boards. For example, it would prefer proposals with components embedded in the substrate and wiring and connections on both sides. At the same time, the NIST also wants to encourage packaging for older manufacturing nodes.
“Whereas traditional boards, silicon or glass interposers and small area substrates are not expected to be in scope for this [Notice of Funding Opportunity], composite substrates using fan-out wafer-level packaging, including flexible and biocompatible substrates, are expected to be entertained,” the notice said.
The substrates should be compatible with “direct attach at fine pitch of advanced node CMOS, legacy nodes, and non-silicon dielets.”
Though unnecessary, NIST encourages proposals that “incorporate embedded substrate features and active and passive devices and through substrate vias.”
The NAPMP is one of the four chip R&D initiatives in the CHIPS and Science Act, all of which are under the purview of NIST. The initiatives are intertwined with each other and create a path from research to commercialization of technologies coming out of the program.
The others include the National Semiconductor Technology Center, which provides funds and the means for the research and development of advanced chips. The technologies developed using the packaging research program could be tested at the NSTC. The NSTC is open to academic institutions, public sector companies, and commercial organizations.
The CHIPS Manufacturing USA Institute is focused on validating the research by creating “digital twins” or running software simulations of how the chips, manufacturing, packaging, substrate, and assembly technologies would perform in an actual physical prototyping facility. Testing a digital twin is standard in commercializing engineering devices, and technologies that pass the NIST tests should be ready to commercialize.
The CHIPS R&D Metrology Program will tie all the pieces together to help manufacturers commercialize technologies. NIST will create standards and provide information that includes materials, data, measurement methods, reference process design kits, and publications.