Advanced chips coming out of factories in the future will become significantly faster with a new interconnect specification that could provide up to 75 times more bandwidth than its predecessors. The Universal Chiplet Interconnect 2.0 (UCIe 2.0) is the latest spec for next-generation chips packed tightly in 3D structures.

The tighter designs will provide unprecedented improvements in speed and power efficiency.

“This is all about keeping things simple — deliver a ton load of bandwidth, but very little power and, … we’re all going to come out way ahead,” said Debendra Das Sharma, chair of the UCIe Consortium, which develops the UCIe specifications.

Facilitates the Move to 3D Designs

The chip-making industry is moving to 3D designs, in which chips are vertically stacked. The 3D structures have mini-chips that perform different functions – called chiplets – which will communicate using the UCIe 2.0 protocol.

“By 2028, chiplets – and systems of chips – will surpass the monolithic die,” said Kevin O’Buckley, senior vice president at Intel Foundry, in a canned public-relations statement published on Intel’s website. Intel didn’t cite the source for the numbers.

The UCIe 1.1 spec was designed for chips in 2D structures, but the 2.0 spec is the first for 3D structures, in which chiplets are stacked next to and on top of each other.

The three-dimensional structure will facilitate more communication channels between chiplets, whereas, in 2D structures, chiplets had to communicate linearly.

3D packaging can compute elements inside chips. Today’s PCs and servers already integrate a mixture of memory, CPUs, GPUs, AI cores, and power-management controls.

“Two main things where you’re going to see a huge impact are bandwidth and power efficiency,” Das Sharma said.

The UCIe 2.0 spec, an open standard, is significantly faster and more power-efficient than the UCIe 1.1 spec, released exactly a year ago.

The UCIe 2.0 spec also makes it viable for chip manufacturers to adopt 3D packaging. TSMC, Samsung, and Intel have their packaging technologies but are also working to support each other’s technologies.

The new spec also opens the door to putting connectors directly into the substrate. For example, many companies plan to implement newer optical interconnects into the substrate so chiplets can communicate at much faster speeds.

UCIe consortium members include the who’s who of device and chip makers, including Nvidia, Intel, AMD, Google, and TSMC. Apple isn’t a member but is expected to adopt 3D structures via TSMC packaging. The consortium was established in 2022.

Faster and More Power Efficient

Chiplets in the 3D structures will have bump pitches of up to 1 micron, which is much closer than the 25-55 micron for the 2.5D structures.

Smaller bump pitches are critical in creating smaller chip packages, allowing for faster bandwidth with more wires connecting chiplets.

“If I have a bump pitch of five microns and I go down to one micron, I have 25 times as many wires in a given area,” Das Sharma said.

The UCIe 2.0 protocol will support a transfer speed of up to 4 GT/s per channel, the same as the UCIe 1.1 spec. But chiplets will have more wires to connect – much like more memory channels – and will be closer to each other.

That increases the bandwidth density and cuts the amount of power required to transfer data.

Each chiplet has its own communications component – a NOC (network on chip) – that speeds up communication between chiplets.

“We start at 4000 gigabytes per second per square millimeter, and we go all the way up to 300,000 gigabytes per second — or 300 terabytes per second — per square millimeter once we hit one micron, a huge amount of bandwidth,” said Das Sharma.

The UCIe 1.1 bandwidth was 165 – 1317 GB/s, but with UCIe 2.0, there’s no limit as more wires will connect chiplets.

The shorter distance between chiplets also makes it magnitudes more power efficient than UCIe 1.1 or industry-standard interconnects.

“This thing helps us with power efficiency because my distance is smaller… and I don’t have much by way of circuitry,” said Das Sharma.

The UCIe 2.0 is expected to draw 0.05 picojoules per bit, going down to 0.01 picojoules per bit at a 1-micron bump pitch.

“If you look into PCI Express or Ethernet, it is 5 to 10 picojoules per bit depending on who is doing the design,” Das Sharma said.

UCIe 2.0 has new tools to manage, discover, and test chiplets throughout their lifecycle. It helps in the process of validation, deployment, and upgrade of chiplets. That will allow chip makers to get a handle on issues relating to manufacturing and performance of chiplets.

“DFX features in UCIe 2.0 provide a standardized approach to improving testability, manufacturability, and reliability across different chiplet designs and manufacturers,” UCIe said in a specification document.

The spec will support CXL, PCIe, and other known interconnects. However, many companies, including Nvidia and Ayar Labs, are developing their own interconnect, which they can put on top of UCIe 2.0.

“You can also map your own proprietary protocol on top of this — some people want to use it for their own scale-up kind of connectivity,” Das Sharma said.

Timeline

There’s no clear timeline for when chips based on UCIe 2.0 will reach the market, but it will take time. The UCIe 1.0 interconnect is still far from being implemented, and Intel showed off a test chip it made on its Intel 3 process last year.

“Individual member companies decide in terms of their own leads … if there is a well-defined spec, they can implement it, and then they will have the products out,” Das Sharma said.

The UCIe Consortium is releasing new specs at a one-year cadence, but there’s no clear timeline for when the follow-up spec to 2.0 will be released.

Das Sharma said there was enough demand for UCIe 2.0, so the spec was released.

UCIe has also established working groups to expand the interconnect to automotive companies looking for faster connections to install in cars.