Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.
Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Emerging supercomputing applications are moving towards a convergence of scientific simulation, data analytics, and learning algorithms, mixed in various ways. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.
This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms.
Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers (excluding references).
Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix.
The templates are available at:
Accepted papers will be published in the IEEE Digital Library through IEEE TCHPC.