SANTA CLARA, Calif., Nov. 22, 2019 — Ayar Labs is pleased to announce that it’s been selected as Intel’s optical I/O solution partner for their recently awarded DARPA PIPES research project. The goal of PIPES (Photonics in Package for Extreme Scalability) is to develop integrated optical I/O solutions co-packaged with next generation FPGA/CPU/GPU and accelerators in Multi-Chip Packages (MCP) to provide extreme data rates (input/output) at ultra-low power over much longer distances than supported by current technology. In the first phase of the project, the Ayar Labs TeraPHY chiplet will be co-packaged with an Intel FPGA using the AIB (Advanced Interconnect Bus) interface and Intel’s EMIB silicon-bridge packaging. “We’re seeing an explosion of Datacenter workloads that have an insatiable demand for bandwidth and the need to connect devices at rack-scale distances,” said Vince Hu, VP of Strategy and Innovation for Intel’s FPGA products. “The best way to do that is with optical interconnect and by using an Ayar Labs chiplet(s), we can achieve very high bandwidth at low latency and low power consumption.”

“Bringing optical connectivity all the way into the CPU/SOC package has long been one of the ‘Holy Grail’ projects in High Performance and Hyperscale Computing, as it unleashes the performance of ever more powerful computing and network processors and removes a major bottleneck and set of constraints in systems architecture and design,” said Charles Wuischpard, CEO of Ayar Labs, “Moreover, the energy consumed in moving data through a system is now very significant and growing, and the best way to manage that is to move the data optically from end to end. We are pleased to be selected by Intel as the optical solution for their DARPA PIPES project and look forward to a multi-year collaboration.”

The TeraPHY chiplet is manufactured on GLOBALFOUNDRIES state-of-the-art 45nm platform, which enabled Ayar Labs to build a monolithic, single-die solution that integrates both electrical and optical photonic circuits and devices on a single chip. “We have worked in close collaboration with Ayar Labs to deliver a new class of integrated electronic, photonics solutions,” said Anthony Yu, vice president of Computing and Wired Infrastructure at GF. “Going forward, we’re excited to work with the pioneers at Ayar Labs to continue disrupting the market by combining our next generation 45nm platform, targeted to future CMOS-based photonics solutions, with their differentiated technology that will push the limits of chip communication bandwidth for high-performance computing, cloud and AI applications.”

As announced earlier this year, Ayar Labs has developed its first fully integrated TeraPHYchiplet and will be demonstrating the solution at the Supercomputing 2019 Conference starting November 18 in Denver, CO. The company is also announcing its Customer Sampling Program with select semiconductor, OEM systems builders, Telco Equipment Manufacturers, and end users starting in early Q1 2020. The program is geared towards demonstrating both the capability of the technology as well as cementing co-design partnerships for future systems architectures in compute, network, and memory. Please contact the company for more details and qualification criteria.

About Ayar Labs

Ayar Labs is disrupting the traditional performance, cost, and efficiency curves of the semiconductor and computing industries by driving a 1000x improvement in interconnect bandwidth density at 10x lower power. Ayar Labs’ patented approach uses industry standard cost-effective silicon processing techniques to develop high speed, high density, low power optical based interconnect “chiplets” and lasers to replace traditional electrical based IO. The company was founded in 2015 and is funded by Playground Global and Founders Fund, as well as strategic investments by GLOBALFOUNDRIES, and Intel Capital. For more information, please visit http://www.ayarlabs.com.

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Source: Ayar Labs