April 19, 2021 — BSC researchers lead eProcessor, a project that will create a 100% European out-of-order (OoO) RISC-V core to produce new embedded High Performance Computing (HPC) products entirely based in Europe.
BSC will coordinate the eProcessor (European, extendable, energy-efficient, energetic, embedded, extensible, Processor Ecosystem) project contributing its experience on hardware design, FPGA emulation, benchmarking, and system simulation tools. More specifically, it will contribute to:
- The design of an energy-efficient, high-performance OoO RISC-V core, which will be implemented as a single-core and dual-core ASICs with off-chip coherent link.
- The design of a RISC-V vector accelerator for HPC workloads for the project’s case studies, exploring different implementations optimized for energy efficiency using a variety of mixed and low-precision data types.
- Explore both traditional HPC workloads as well as emerging High Performance Data Analytics (HPDA) workloads such as Artificial Intelligence (AI) and bioinformatics applications
The eProcessor project consortium is composed of the Barcelona Supercomputing Center, Chalmers University of Technology, Foundation for Research and Technology- Hellas, Universita degli Studi di Roma La Sapienza, Cortus, Christmann Informationstechnik, Universität Bielefeld, Extoll GmbH, Thales, and Exapsys.
The project aims to build a new open source OoO processor, and its objective is to deliver the first completely open source European full-stack ecosystem based on this new RISC-V CPU. The technology will be extendable (open source), energy efficient (low power), extreme-scale (high performance), suitable for uses in HPC and embedded applications, and extensible (easy to add on-chip and/or off-chip components).
eProcessor combines cutting edge research, utilizing SW/HW co-design to achieve sustained processor and system performance for sparse and mixed-precision HPC and HPDA workloads by combining a high performance low power architecture with low-power circuit techniques, in an OoO processor core with novel, adaptive on-chip memory structures, and on-chip memory management, as well as fault tolerance features. These software-hardware co-design solutions span the full stack from applications to runtimes, tools, Operating system (OS), and the CPU and accelerators.
As shown in the figure above, the technology developed in the ecosystem includes:
- Traditional HPC applications for scientific computing problems that use solvers based on linear algebra and numerical methods with dense and sparse data structures from the NAS benchmark suite and others.
- HPDA-AI applications with real use cases built on top of the European Distributed Deep Learning Library (EDDLL), which will impact critical areas, ranging from precision medicine to image recognition.
- HPDA-Bioinformatics applications that focus on high-performance genomic processing pipelines, sequence alignment, and pattern matching.
- Runtimes and compilers that support the HPC, and HPDA domains at the system software layer by targeting the main programming frameworks used in these domains, such as OpenMP for HPC, Spark for HPDA– Bioinformatics, and Tensorflow for HPDA-AI.
- Performance and optimization tools that provide application insight to help extract the most performance and efficiency present in these HPC and HPDA applications.
- An OS that will use and extend an existing open source Linux platform. An important goal will be to minimize overheads and provide consistent noise-free execution.
- Explore options for on-chip functional units, on-chip coprocessors, and off-chip accelerators targeting vector accelerators and functional units for traditional HPC applications and emerging HPDA applications.
- Enable an on-chip coherent multicore SoC, as well as an off-chip coherent link for processors or accelerators.
- Two silicon tapeouts: A single core and multicore implementation of an open source OoO RISC-V CPU.
- In collaboration with the MareNostrum Experimental Exascale Platform (MEEP) project, FPGA emulation that will be used to enable early software development and pre-silicon validation.
- Extending the LEGaTO Project’s infrastructure by producing a LEGaTO-compatible eProcessor CPU PCB.
“The eProcessor project is developing a new OoO RISC-V CPU and will be leveraging and extending the work done in multiple European projects. By doing so, eProcessor can achieve a Technical Readiness Level (TRL) of between 5-7. Furthermore, working with our industrial partners provides a direct path to commercialization. Achieving the goals of eProcesor can only be done with a combination of SW simulation, HW emulation using FPGAs, and real ASIC prototypes that demonstrate the hardware and software’s full-stack feasibility. All these efforts translate into the first step of many that are required to build a vibrant open software and hardware ecosystem in Europe” states John D. Davis, Director of the Laboratory for Open Computer Architecture at BSC.
The eProcessor project will address the HPC and HPDA domains and contribute to the realization of European exascale system architectures by (a) developing open source “made-in-EU” hardware and software technologies; (b) facilitating a large FPGA emulation system to quickly answer “what-if” research questions and perform performance explorations for future systems, and (c) implementing European hardware components in ASICs to offer silicon-proven IPs.
The project supports the objective of EuroHPC JU to develop innovative supercomputing technologies and applications to underpin a world-class European HPC ecosystem as well as its aim to improve quality of life, advance science, boost industrial competitiveness, and ensure Europe’s technological autonomy.
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. The RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
BSC is a member of the RISC-V International and organized the official RISC-V Workshop in May 2018. Moreover, John D. Davis, the Director of the Laboratory for Open Computer Architecture at BSC, is the Chair of the RISC-V International Special Interest Group on High-Performance Computing (SIG-HPC). As such, he also participates in the RISC-V Technical Steering Committee (TSC). Many other partners in eProcessor are also members of RISC-V International.
The European High Performance Computing Joint Undertaking (EuroHPC) launches calls for proposals to fund research and innovation activities that will help Europe remain globally competitive in supercomputing.
The mission of the EuroHPC JU is to develop, deploy, extend and maintain an integrated world-class supercomputing and data infrastructure in the European Union (EU) and develop and support a highly competitive and innovative HPC ecosystem.
The EuroHPC JU aims at equipping the EU by early 2021 with an infrastructure of petascale (capable of at least 1015 calculations per second) and precursor to exascale supercomputers (capable of at least 1018calculations per second), and developing the necessary technologies and applications for reaching full exascale capabilities around 2022 / 2023.
The eProcessor project has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 956702. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Spain, Sweden, Greece, Italy, France, and Germany.