Cadence Collaborates With TSMC to Accelerate 5nm FinFET Innovation

April 22, 2019

SAN JOSE, Calif., April 22, 2019 — Cadence Design Systems, Inc. today announced that it has collaborated with TSMC to enable customers’ production delivery of next-generation system-on-chip (SoC) designs for mobile, high-performance computing (HPC), 5G and artificial intelligence (AI) applications on TSMC’s 5nm FinFET process technology. As part of the collaboration, the Cadence digital, signoff and custom/analog tools have been certified for Design Rule Manual (DRM) and SPICE v1.0, and Cadence IP has been enabled for the TSMC 5nm process. The corresponding process design kits (PDKs) featuring integrated tools, flows and methodologies are now available for traditional and cloud-based environments. Additionally, mutual customers have already completed several tapeouts using Cadence tools, flows and IP for full production development on the TSMC 5nm process technology.

To learn more about the Cadence full-flow digital and signoff advanced-node solutions, visit www.cadence.com/go/tsmc5nmds. For information about the Cadence custom/analog advanced-node solutions, visit www.cadence.com/go/tsmc5nmca. For information about Cadence IP, visit www.cadence.com/go/tsmc5nmip.

5nm Digital and Signoff Tool Certification

Cadence delivered a fully integrated digital implementation and signoff tool flow, which has been certified on TSMC’s industry-leading 5nm process that has the benefits of process simplification provided by extreme ultraviolet (EUV) lithography. The Cadence full-flow includes the Innovus Implementation System, Liberate Characterization Portfolio, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus Verification System.

The Cadence digital and signoff tools that have been optimized for TSMC’s 5nm process technology provide EUV support at key layers and associated new design rules, which enable mutual customers to reduce iterations and achieve performance, area, and power (PPA) improvements.Some of the newest enhancements for the 5nm process include predictive via-pillar-aware synthesis structuring with the Genus Synthesis Solution as well as a pin-access control routing method for cell electromigration (EM) handling in the Innovus Implementation System and Tempus ECO and also statistical EM budgeting analysis support in the Voltus IC Power Integrity Solution. The newly certified Pegasus Verification System supports 5nm rule decks for all TSMC physical verification flows including DRC, LVS and metal fill.

5nm Custom/Analog Tool Certification

The Cadence custom/analog tools certified on TSMC’s industry-leading 5nm process technology include the Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option, Spectre Circuit Simulator, Voltus-Fi Custom Power Integrity Solution, Pegasus Verification System as well as the Virtuoso® custom IC design platform, which includes the Virtuoso Layout Suite EXL, Virtuoso Schematic Editor and Virtuoso ADE Product Suite.

The Virtuoso R&D team has an ongoing and rich collaboration with the Cadence IP Group, developing 5nm mixed-signal IP using a state-of-the-art custom design methodology built on the latest Virtuoso design platform. By continually enhancing the design methodologies and capabilities included with the Virtuoso Advanced-Node and Methodology Platform for TSMC’s advanced-node processes, including the 5nm process, customers can achieve better custom physical design throughput versus traditional non-structured design methodologies.

The new Virtuoso Advanced-Node and Methodology Platform (ICADVM 18.1) consists of features and functionality required for creating 5nm designs, which include an accelerated, row-based custom placement and routing methodology that enables users to improve productivity and better manage complex design rules. Cadence introduced several new features that support the 5nm process including stacked gate support, universal poly grid snapping, area-based rule support, asymmetric coloring and voltage-dependent rule support, analog cell support and support for various new devices and design constraints that are part of TSMC’s 5nm technology offering.

5nm IP Enablement

Cadence is developing a differentiated advanced-node IP portfolio to support TSMC’s 5nm process, which includes a high-performance memory subsystem, very high-speed SerDes and high-performance analog to meet the demands of HPC, machine learning (ML) and 5G base stations. With the release of TSMC’s 5nm design infrastructure, Cadence and TSMC are actively engaged with customers and enabling next-generation SoC development by addressing the latest IP requirements for evolving application areas.

“TSMC’s 5nm technology offers our customers the industry’s most advanced technology to address the growing demand for computing power driven by AI and 5G,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “By collaborating closely with Cadence, we’re enabling customers to effectively differentiate themselves and deliver designs to market faster using our latest technologies.”

“We’re continuing to broaden our collaboration with TSMC to facilitate 5nm FinFET adoption, giving customers access to the latest tools and IP for advanced process design creation,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Our R&D team has focused heavily on developing new features and performance improvements so that our digital and signoff and custom/analog tools and IP can be used with complete confidence, enabling customers to achieve first-pass silicon success and deliver end products within aggressive time-to-market schedules.”

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For.


Source: Cadence

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

BlueField SmartNIC Backs Transformation to Bare Metal Kubernetes

May 21, 2019

Hardware vendors are betting the transition to 5G wireless networks supporting myriad connected consumer and industrial devices also will accelerate the shift to heavy-duty bare-metal servers as a way to provision cloud- Read more…

By George Leopold

HPE to Acquire Cray for $1.3B

May 17, 2019

Venerable supercomputer pioneer Cray Inc. will be acquired by Hewlett Packard Enterprise for $1.3 billion under a definitive agreement announced this morning. The news follows HPE’s acquisition nearly three years ago o Read more…

By Doug Black & Tiffany Trader

China Establishes Seventh National Supercomputing Center

May 16, 2019

Chinese media is reporting that China will construct a new National Supercomputer Center in Zhengzhou, in central China's Henan Province. The new Zhengzhou facility will house a 100-petaflops supercomputer and will be ta Read more…

By Staff report

HPE Extreme Performance Solutions

HPE and Intel® Omni-Path Architecture: How to Power a Cloud

Learn how HPE and Intel® Omni-Path Architecture provide critical infrastructure for leading Nordic HPC provider’s HPCFLOW cloud service.

For decades, HPE has been at the forefront of high-performance computing, and we’ve powered some of the fastest and most robust supercomputers in the world. Read more…

IBM Accelerated Insights

Smarter EDA: Leveraging New Technologies for Product Verification

There is perhaps no sector more competitive than the modern electronics industry. Macro-trends, including artificial intelligence, 5G, and the internet of things (IoT), continue to propel dramatic growth. Read more…

Interview with 2019 Person to Watch Ken King

May 16, 2019

Today, as the final installment of our HPCwire People to Watch focus series, we present our interview with Ken King, general manager of OpenPOWER for the IBM Systems Group. Ken is responsible for building and managing t Read more…

By HPCwire Editorial Team

HPE to Acquire Cray for $1.3B

May 17, 2019

Venerable supercomputer pioneer Cray Inc. will be acquired by Hewlett Packard Enterprise for $1.3 billion under a definitive agreement announced this morning. T Read more…

By Doug Black & Tiffany Trader

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

CCC Offers Draft 20-Year AI Roadmap; Seeks Comments

May 14, 2019

Artificial Intelligence in all its guises has captured much of the conversation in HPC and general computing today. The White House, DARPA, IARPA, and Departmen Read more…

By John Russell

Cascade Lake Shows Up to 84 Percent Gen-on-Gen Advantage on STAC Benchmarking

May 13, 2019

The Securities Technology Analysis Center (STAC) issued a report Friday comparing the performance of Intel's Cascade Lake processors with previous-gen Skylake u Read more…

By Tiffany Trader

Nvidia Claims 6000x Speed-Up for Stock Trading Backtest Benchmark

May 13, 2019

A stock trading backtesting algorithm used by hedge funds to simulate trading variants has received a massive, GPU-based performance boost, according to Nvidia, Read more…

By Doug Black

ASC19: NTHU Returns to Glory

May 11, 2019

As many of you Student Cluster Competition fanatics know by now, Taiwan’s National Tsing Hua University (NTHU) won the gold medal at the recently concluded AS Read more…

By Dan Olds

Intel 7nm GPU on Roadmap for 2021, OneAPI Coming This Year

May 8, 2019

At Intel's investor meeting today in Santa Clara, Calif., the company filled in details of its roadmap and product launch plans and sought to allay concerns about delays of its 10nm chips. In laying out its 10nm and 7nm timelines, Intel revealed that its first 7nm product would be... Read more…

By Tiffany Trader

Ten Great Reasons to Build the 1.5 Exaflops Frontier

May 7, 2019

It’s perhaps obvious that the fundamental reason for building expensive exascale computers is to drive science and industry forward, realizing the resulting b Read more…

By John Russell

Cray, AMD to Extend DOE’s Exascale Frontier

May 7, 2019

Cray and AMD are coming back to Oak Ridge National Laboratory to partner on the world’s largest and most expensive supercomputer. The Department of Energy’s Read more…

By Tiffany Trader

Graphene Surprises Again, This Time for Quantum Computing

May 8, 2019

Graphene is fascinating stuff with promise for use in a seeming endless number of applications. This month researchers from the University of Vienna and Institu Read more…

By John Russell

Why Nvidia Bought Mellanox: ‘Future Datacenters Will Be…Like High Performance Computers’

March 14, 2019

“Future datacenters of all kinds will be built like high performance computers,” said Nvidia CEO Jensen Huang during a phone briefing on Monday after Nvidia revealed scooping up the high performance networking company Mellanox for $6.9 billion. Read more…

By Tiffany Trader

ClusterVision in Bankruptcy, Fate Uncertain

February 13, 2019

ClusterVision, European HPC specialists that have built and installed over 20 Top500-ranked systems in their nearly 17-year history, appear to be in the midst o Read more…

By Tiffany Trader

It’s Official: Aurora on Track to Be First US Exascale Computer in 2021

March 18, 2019

The U.S. Department of Energy along with Intel and Cray confirmed today that an Intel/Cray supercomputer, "Aurora," capable of sustained performance of one exaf Read more…

By Tiffany Trader

Intel Reportedly in $6B Bid for Mellanox

January 30, 2019

The latest rumors and reports around an acquisition of Mellanox focus on Intel, which has reportedly offered a $6 billion bid for the high performance interconn Read more…

By Doug Black

Looking for Light Reading? NSF-backed ‘Comic Books’ Tackle Quantum Computing

January 28, 2019

Still baffled by quantum computing? How about turning to comic books (graphic novels for the well-read among you) for some clarity and a little humor on QC. The Read more…

By John Russell

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

Deep500: ETH Researchers Introduce New Deep Learning Benchmark for HPC

February 5, 2019

ETH researchers have developed a new deep learning benchmarking environment – Deep500 – they say is “the first distributed and reproducible benchmarking s Read more…

By John Russell

IBM Bets $2B Seeking 1000X AI Hardware Performance Boost

February 7, 2019

For now, AI systems are mostly machine learning-based and “narrow” – powerful as they are by today's standards, they're limited to performing a few, narro Read more…

By Doug Black

Arm Unveils Neoverse N1 Platform with up to 128-Cores

February 20, 2019

Following on its Neoverse roadmap announcement last October, Arm today revealed its next-gen Neoverse microarchitecture with compute and throughput-optimized si Read more…

By Tiffany Trader

Intel Launches Cascade Lake Xeons with Up to 56 Cores

April 2, 2019

At Intel's Data-Centric Innovation Day in San Francisco (April 2), the company unveiled its second-generation Xeon Scalable (Cascade Lake) family and debuted it Read more…

By Tiffany Trader

France to Deploy AI-Focused Supercomputer: Jean Zay

January 22, 2019

HPE announced today that it won the contract to build a supercomputer that will drive France’s AI and HPC efforts. The computer will be part of GENCI, the Fre Read more…

By Tiffany Trader

In Wake of Nvidia-Mellanox: Xilinx to Acquire Solarflare

April 25, 2019

With echoes of Nvidia’s recent acquisition of Mellanox, FPGA maker Xilinx has announced a definitive agreement to acquire Solarflare Communications, provider Read more…

By Doug Black

Nvidia Claims 6000x Speed-Up for Stock Trading Backtest Benchmark

May 13, 2019

A stock trading backtesting algorithm used by hedge funds to simulate trading variants has received a massive, GPU-based performance boost, according to Nvidia, Read more…

By Doug Black

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This