Enyx Premieres TCP and UDP Offload Engines for Intel Stratix 10 FPGA On REFLEX CES XpressGXS10-FH200G Board

November 15, 2017

DENVER, Nov. 15, 2017 — Enyx, a world-class pioneer in ultra-low latency FPGA-based technology and solutions, is pleased to announce its enterprise-class TCP/IP, UDP/IP and MAC network connectivity Intellectual Property (IP) Cores for FPGAs and SoCs support for the high-performance REFLEX CES XpressGXS10-FH200G PCIe Board, which features a Stratix 10 GX FPGA from Intel’s new top-of-the-line 14nm Stratix 10 family

Enyx network connectivity IP Cores are addressing the growing throughput and hardware acceleration needs of the datacenter industry and are performing network protocol offloading for applications, such as network security enabled NICs, smart NICs, high performance data distribution, custom packet filtering and high bandwidth bridges. Enyx also provides custom project implementation through Enyx Design Services as part of a complete and customized Smart NIC or Smart Switch solution.

“We are pleased to collaborate with our valued partner REFLEX CES to offer the industry-first TCP and UDP full hardware stacks on Intel’s new, cutting-edge Stratix 10 FPGAs,” says Eric Rovira Ricard, VP Business Development North America at Enyx. “Intel is making FPGA technology ready for data centers, opening new areas for hardware offloading applications in high performance computing, and Enyx is proud to provide the most mature and feature rich network protocol stacks for seamless, FPGA-enabled network connectivity on the latest devices.”

“We are delighted to work with Enyx to offer the best-in-class UDP & TCP IP low latency reference design on our Stratix 10 FPGA board first to market for the Finance and Networking applications, and therefore providing a fast and trusted solution,” said Eric Penain, Chief Business Officer at REFLEX CES.

Enyx nxTCP and nxUDP IP Cores feature full RTL Layers 2, 3, 4 implementations with integrated 40G/25G/10G/1G MAC, compliant with the IEEE 802.3 standards, supporting ARP, IPv4, ICMP, IGMP and TCP/UDP protocols. nxTCP and nxUDP are designed to work seamlessly on Intel (formerly Altera) and Xilinx FPGA and SoC designs. Enyx TCP implementation on Intel Stratix 10 GX devices feature latencies of less than 60 ns in transmission and 110 ns in reception and can also manage up to 32,768 TCP sessions in parallel.

REFLEX CES XpressGXS10-FH200G is the first commercially available PCIe board supporting the 14nm Intel Stratix 10 FPGA family. REFLEX CES XpressGXS10-FH200G PCIe board includes the biggest 2800 KLE Stratix 10 density for processing intensive and various data algorithms with its mix of memory capabilities in DDR4 and QDR2+. It has an optical interface capability of 200Gbit via two QSFP28 cages and uses PCIe gen3 x16. An additional 200Gbit board-to-board interface is provided using a firefly connection. The footprint is compatible with SoC FPGA’s enabled HPS access via the Ethernet interface on the PCIe bracket side. REFLEX CES is a certified board partner of Enyx.

Starting in 2018, the Intel Stratix 10 version downloadable package will be available and will include a reference design for the REFLEX CES XpressGXS10-FH200G PCIe board.

Enyx made this announcement today at the SC17 conference in Denver where it is currently presenting its technology product line and services.

About Enyx

Enyx is a leading developer and provider of FPGA-based ultra-low latency technologies and solutions. Enyx Technology & Design Services division provides design services and connectivity IP cores for FPGA and SoC, for tailored Smart NICs and Smart Switches. Enyx Technology & Design Services division has engaged with over 50 customers world-wide, including hedge funds, exchanges, top-tier investment banks, telecom operators, research labs, universities, and technology manufacturers for the defense, military, aeronautics, aerospace and high-performance computing industries.

For more information, visit www.enyx.com

About REFLEX CES

Recognized for its expertise in high-speed applications, analog and hardened systems, REFLEX CES has become a leading partner with major industrial companies. REFLEX CES simplifies the adoption of FPGA technology with its leading-edge FPGA-based custom embedded and complex systems. REFLEX CES FPGA network platforms enable better flexibility and ease of programming, offering a faster and most powerful board, and reducing the customers’ technology risks and time to market. The company provides FPGA COTS boards for several markets, including the Finance market where Ultra Low Latency capability is a key element, and other markets like Networking.


Source: Enyx

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

TACC Researchers Test AI Traffic Monitoring Tool in Austin

December 13, 2017

Traffic jams and mishaps are often painful and sometimes dangerous facts of life. At this week’s IEEE International Conference on Big Data being held in Boston, researchers from TACC and colleagues will present a new Read more…

AMD Wins Another: Baidu to Deploy EPYC on Single Socket Servers

December 13, 2017

When AMD introduced its EPYC chip line in June, the company said a portion of the line was specifically designed to re-invigorate a single socket segment in what has become an overwhelmingly two-socket landscape in the d Read more…

By John Russell

Microsoft Wants to Speed Quantum Development

December 12, 2017

Quantum computing continues to make headlines in what remains of 2017 as tech giants jockey to establish a pole position in the race toward commercialization of quantum. This week, Microsoft took the next step in advanci Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

Explore the Origins of Space with COSMOS and Memory-Driven Computing

From the formation of black holes to the origins of space, data is the key to unlocking the secrets of the early universe. Read more…

ESnet Now Moving More Than 1 Petabyte/wk

December 12, 2017

Optimizing ESnet (Energy Sciences Network), the world's fastest network for science, is an ongoing process. Recently a two-year collaboration by ESnet users – the Petascale DTN Project – achieved its ambitious goal t Read more…

AMD Wins Another: Baidu to Deploy EPYC on Single Socket Servers

December 13, 2017

When AMD introduced its EPYC chip line in June, the company said a portion of the line was specifically designed to re-invigorate a single socket segment in wha Read more…

By John Russell

Microsoft Wants to Speed Quantum Development

December 12, 2017

Quantum computing continues to make headlines in what remains of 2017 as tech giants jockey to establish a pole position in the race toward commercialization of Read more…

By Tiffany Trader

HPC Iron, Soft, Data, People – It Takes an Ecosystem!

December 11, 2017

Cutting edge advanced computing hardware (aka big iron) does not stand by itself. These computers are the pinnacle of a myriad of technologies that must be care Read more…

By Alex R. Larzelere

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Microsoft Spins Cycle Computing into Core Azure Product

December 5, 2017

Last August, cloud giant Microsoft acquired HPC cloud orchestration pioneer Cycle Computing. Since then the focus has been on integrating Cycle’s organization Read more…

By John Russell

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

HPE In-Memory Platform Comes to COSMOS

November 30, 2017

Hewlett Packard Enterprise is on a mission to accelerate space research. In August, it sent the first commercial-off-the-shelf HPC system into space for testing Read more…

By Tiffany Trader

SC17 Cluster Competition: Who Won and Why? Results Analyzed and Over-Analyzed

November 28, 2017

Everyone by now knows that Nanyang Technological University of Singapore (NTU) took home the highest LINPACK Award and the Overall Championship from the recently concluded SC17 Student Cluster Competition. We also already know how the teams did in the Highest LINPACK and Highest HPCG competitions, with Nanyang grabbing bragging rights for both benchmarks. Read more…

By Dan Olds

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

Leading Solution Providers

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This