Intel Outlines Its Upcoming AI and HPC Sessions at ISC

June 19, 2018

June 19, 2018 — Intel is excited to be a part of ISC High Performance 2018 in Frankfurt, Germany, June 25–28. ISC brings together academic and commercial disciplines to share knowledge in the field of high performance computing. Intel’s presence at the event will include keynotes, sessions, and booth demos that will be focused on the future of HPC technology, including Artificial Intelligence (AI) and visualization. Also featured in the Intel booth: The Intel Collaboration Hub hosting eight in-booth panel discussions and 25 Intel and partner presentations.

Throughout Intel’s presence at ISC, they will showcase how the industry and the world are entering an advanced era of HPC that now includes AI technologies. The data and algorithmic innovations powered with deep learning have led to a sharp increase in the need for compute. As deep learning and other AI techniques evolve with massive data sets and image sizes, they will continue to require high compute power that scales to the size of HPC infrastructures. Intel will showcase how it’s helping AI developers, data scientists and HPC programmers transform industries such as healthcare, retail and finance by tapping into HPC to power the AI solutions of today and the future.

Key Intel Sessions

Keynote: Supercomputing Circa 2025
Dr. Raj Hazra, Corporate Vice President at Intel, will discuss emerging technologies that will accelerate discovery and innovation. The convergence of AI, analytics and simulation and modeling provide new opportunities and challenges for every organization and will require new system architecture for HPC. Dr. Hazra will explore new system level architecture approaches that will help global HPC leaders reach new breakthroughs in system performance and capabilities.

Speaker: Raj Hazra, Corporate Vice President at Intel
Date: Monday, June 25, 2018
Time: 6:00 to 6:45 p.m.
Location: Panorama 2, Forum

Keynote at the HP-CAST Event: New Era in HPC
Trish Damkroger, Vice President, Data Center Group, General Manager, Technical Computing Initiative, Enterprise and Government at Intel will keynote at the HP-CAST, HPE’s user group meeting for high performance computing on the New Era in HPC. She will discuss the changing landscape of technical computing, key trends in HPC, and the convergence of HPC-AI-HPDA that is transforming the industry and ensuring technical computing continues to fulfill its potential as a scientific tool for insight and innovation. Trish will also provide an overview of Intel’s technical computing strategy, products, and ecosystem collaborations that are driving this transformation.

Speaker: Trish Damkroger, Vice President, Data Center Group, General Manager, Technical Computing Initiative, Enterprise and Government at Intel
This keynote will take place at the HP-CAST event.

Machine Learning Day at ISC
Within the last few years, machine learning has become a vital topic within the HPC community. Vendors see the development as an opportunity to expand their high-performance solutions into a new and fast-growing market, and traditional HPC users are incorporating these techniques into their workflows to speed processing and extract greater insights. ISC High Performance will provide a special focus on this subject matter with a one-day track on Wednesday, June 27, where Pradeep Dubey, Intel Fellow at Intel Labs and the Director of the Parallel Computing Lab, will speak in the following session:

Session: On Scale-out Deep Learning Training for Cloud and HPC
Pradeep Dubey, Intel Fellow at Intel Labs and the Director of the Parallel Computing Lab will be one of the featured speakers for Machine Learning Day at ISC. He will discuss how the exponential growth of Artificial Intelligence (AI) and Deep Learning (DL) has accelerated the need for training deep neural networks in hours or even minutes. This can only be achieved through scalable and efficient distributed training, since a single node/card cannot satisfy the compute, memory, and I/O requirements of today’s state-of-the-art neural networks. However, scaling Stochastic Gradient Descent (SGD) is still a challenging problem and requires continued research/development. This entails innovations spanning algorithms, frameworks, communication libraries, and system design. In this talk, Pradeep will describe the philosophy, design, and implementation of Intel Machine Learning Scalability Library (MLSL), support in popular DL frameworks, and present proof-points demonstrating scaling DL training on 100s to 1000s of nodes across Cloud and HPC systems.

Speaker: Pradeep Dubey, Intel Fellow at Intel Labs
Session: Scalable Machine Learning Systems
Time: Wednesday, June 27, 1:45 to 2:15 p.m.
Location: Panorama 2

Intel booth activities located in Messe Frankfurt, Hall 3 (upper level) F-930

The Intel Collaboration Hub, located inside the Intel booth, will be the place to get updates from Intel, meet experts, experience panel discussions, and see the latest from Intel. Below are two panel discussion highlights. Click the link below to see the full schedule:

Panel: Intel Select Solutions – Intro to Professional Visualization 
Hosts: Jeff Jeffers, Senior Director, Senior Principle Engineer, Visualization Engineering at Intel; Ullrich Becker-Lemgau, Technical Marketing Engineer, Intel; and Werner Krotz-Vogel, Technical Marketing Manager, Intel
Time: 11 a.m.
Location: Intel Collaboration Hub inside the Intel booth

Panel: Convergence of AI and HPC
Host: Binay Ackalloor, Director, Business Development, Artificial Intelligence & Machine Learning at Intel
Time: 12 p.m.
Location: Intel Collaboration Hub inside the Intel booth

Please see the full schedule of the Intel Collaboration Hub speakers and panels below.

Intel ISC Booth Demos

Demo: AI on IA—Brain Tumor Segmentation
See an interactive demo of a solution built by Intel to help identify brain tumors. This solution uses deep CNNs to segment brain tumors in 2D MRI images, using 2016 Brain and Tumor Segmentation (BraTS) dataset and containing 31,000 2D MRI scans at 240×240 pixel resolution. Each brain has 255 slices, and the dataset represents ~120 individuals. Intel will deliver a flexible deployment architecture that provides great performance and T.C.O for GE Imaging C.T. group to deliver deep learning applications for their imaging modalities. The result is a trained model that is able to segment brain tumors just as well as a neuroradiologist. Intel then passes along the final MRI images and segmentation maps to EchoPixel for visualization.

Demo: Defined Visualization
See the latest Intel Select Solution that uses software-defined visualization and state-of-the-art Intel ingredients for modeling with visualization of even the most complex and large data sizes. The demo will showcase automotive CFD Analysis with OpenFOAM, ParaView v5.5 using OSPRay to demonstrate high visual fidelity of software-defined visualization using ray tracing to display an animation of airflow over a moving vehicle.

Demo: Application Acceleration with FPGA 
This demo is built around the Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA (Intel PAC with Intel Arria 10 GX FPGA) and demonstrates how FPG-based processing provides high performance and low power. See how to dynamically configure an FPGA to run multiple functions or workloads using partial reconfiguration. The workloads run on the FPGA will be file compression, genome sequencing, image recognition, and video segmentation. The demo will use the Intel PAC with Intel Arria 10 GX FPGA, a robust collection of software, firmware, and tools to make it easier to use Intel FPGAs for workload optimization. The Acceleration Stack abstracts the FPGA design, enabling software application developers to leverage the benefits of FPGAs.

Demo: Distributed Deep Reinforcement Learning on CPU
An Adam optimization algorithm with a batch size of up to 2048 is a viable choice for carrying out large scale machine learning computations. See how this optimization is used to train an Atari agent to play games, which resulted in substantially decreasing the training time. The results were collected using a multi-node Intel Xeon processor-based cluster (formerly codenamed Haswell) and the optimized TensorFlow for Intel architecture. We will demonstrate the progress of the training model, including detailed hardware configuration and software stack, as well as visualization of all critical parameters of the training algorithm and their progress over time.

Attendees can engage with Intel in various sessions (see the ISC schedule) and in the Intel booth (Messe Frankfurt, Hall 3 (upper level) F-930).

The full Intel Collaboration Hub schedule (taking place in Messe Frankfurt, Hall 3 (upper level) F-930) can be found at this link.


Source: Intel

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