OpenHW Group Announces CORE-V Family of Open-Source Cores for Use in High Volume Production SoCs

June 9, 2019

OTTAWA, Ontario and ZURICH, June 9, 2019 — A new not-for-profit global organization aims to boost the adoption of open-source processors by providing a platform for collaboration, creating a focal point for ecosystem development, and offering open-source IP for processor cores.

Headed by Founder and CEO, Rick O’Connor, the OpenHW Group has already recruited 13 sponsor organizations and expects this to grow to 25 by the end of 2019. OpenHW Group is a member of the RISC-V Foundation of which O’Connor was Executive Director until May this year, and has entered into a strategic partnership with the Eclipse Foundation, a global community for open-source software collaboration and innovation.

Inaugural OpenHW sponsors include Alibaba, Bluespec, CMC Microsystems, Embecosm, ETH Zurich (University), GreenWaves, Imperas, Metrics, Mythic AI, NXP, Onespin, Silicon Labs and Thales.

The OpenHW Group will serve developers of processor cores and hardware and software engineers who design SoCs. The advent of open ISAs such as RISC-V has encouraged organizations throughout the world to take a fresh look at open-source processor development. For these organizations, the OpenHW Group aims to drive greater awareness, understanding and availability of open-source processor implementations.

O’Connor explains, “If you design or are looking for open-source processor IP, OpenHW Group is an organization for collaborating with like-minded engineers. If you’re an SoC designer, you don’t have to design from scratch; we will help you accelerate your design process by supplying you with a growing range of proven processor IP options, all available within an expanding, high-quality ecosystem. For example, for RISC-V-based processors, we’re introducing the CORE-V family of cores, which supports system-on-chip (SoC) hardware and software designers with a quality and manufacturability assurance when adopting RISC-V processor core IP.”

Rob Oshana, Chairman of the Board, OpenHW Group and VP Software Engineering, NXP said, “The electronics industry is embracing open-source processor technologies at an unprecedented rate. At NXP we believe there’s a need to create a deep ecosystem to support adoption of the RISC-V ISA. This includes various components – middleware, stacks and tools – all aligned to move the architecture forward. I’m pleased to serve as Chairman of the OpenHW Group board to help realise this goal.”

Sponsor and partner testimonials:

Alessandro Piovaccari, Board Director OpenHW Group and CTO of Silicon Labs
“Within the next few years, most of the billions of SoCs in our smart, connected world will contain many specialized cores to address various tasks from subsystems supervision, to security and machine learning. I’m delighted to join the board of the OpenHW Group because I believe the CORE-V Family of open-source RISC-V cores will be vital in providing robust and accessible processors to address this need, which will ultimately help accelerate innovation in the IoT.”

Xiaoning Qi, Ph.D., Board Director OpenHW Group and VP of Alibaba Group
“Alibaba Group values open innovation that drives the internet technology forward. I am honoured to join the board of the OpenHW Group and support the development of open-source processor technology driving IoT, AI, ML and server platforms.”

Charlie Hauck, Board Director OpenHW Group and CEO, Bluespec
“Bluespec is dedicated to making RISC-V safe and easy to use. We’re excited to see the growing adoption of RISC-V open-source processors and the new age of innovation that it will enable. We look forward to contributing our expertise to the board of the OpenHW Group, whose aims we fully endorse.”

Luca Benini, Professor and Chair of Digital Circuits & Systems, ETH Zurich
“In today’s semiconductor industry, collaboration is crucial to rapid innovation. For ETH Zurich and University of Bologna, and the continuing development of our PULP Platform, the OpenHW Group will provide an invaluable forum for accelerating our research and innovation activities.  Hence, we are extremely proud to contribute the cores from our PULP Platform into the OpenHW Group family of Core-V cores.”

Calista Redmond, CEO RISC-V Foundation
“As we continue to cultivate the RISC-V community, we are excited to welcome organizations like OpenHW group as a forum for ongoing innovation and collaboration serving the many stakeholders in the RISC-V revolution.”

Dave Patterson, UC Berkeley Professor, Turing Laureate, & Vice-Chair RISC-V Foundation
“As a passionate believer in open innovation, I’m delighted to see Rick leverage his successful experience with the RISC-V Foundation to lead the OpenHW Group, which will benefit the whole semiconductor industry by making open-source processor technology more accessible to a wider audience.”

Mike Milinkovich, Executive Director of the Eclipse Foundation
“The Eclipse Foundation has been at the forefront of community-based open source software development for many years.We are pleased to provide our guidance and expertise for the launch of the OpenHW Group and for the ongoing development of open source processor cores and related subsystem IP, tools, and software.”

Philipp Wagner, Director at the FOSSi Foundation
“The FOSSi Foundation welcomes the OpenHW Group to the Free and Open Source Silicon ecosystem. Their sustained development the CORE-V Family of open-source RISC-V cores will be of great benefit to the community. We applaud their efforts to explore an open and meritocracy-based contribution model for free/open silicon, enabling individuals to work as equals together with companies for the good of the whole ecosystem.”

About the OpenHW Group

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software such as the CORE-V Family of cores. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

CORE-V is a series of RISC-V based open-source cores with associated processor subsystem IP, tools and software for electronic system designers. The CORE-V family provides quality core IP in line with industry best practices. The IP is available in both silicon and FPGA optimized implementations. These cores can be used to facilitate rapid design innovation and ensure effective manufacturability of high-volume production SoCs.

Website: OpenHWGroup.org


Source: OpenHW Group

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Better Scientific Software: Turn Your Passion into Cash

September 13, 2019

Do you know your way around scientific software and programming? You think you can contribute to the community by making scientific software better? If so, then the Better Scientific Software (BSSW) organization wants yo Read more…

By Dan Olds

Google’s ML Compiler Initiative Advances

September 12, 2019

Machine learning models running on everything from cloud platforms to mobile phones are posing new challenges for developers faced with growing tool complexity. Google’s TensorFlow team unveiled an open-source machine Read more…

By George Leopold

HPC Perspectives with Dr. Seid Koric

September 12, 2019

Brendan McGinty, director of Industry for the National Center for Supercomputing Applications (NCSA), University of Illinois at Urbana-Champaign, kicks off the first in a series of pieces profiling leaders in high performance computing (HPC), writing for the... Read more…

By Brendan McGinty

AWS Solution Channel

A Guide to Discovering the Best AWS Instances and Configurations for Your HPC Workload

The flexibility and heterogeneity of HPC cloud services provide a welcome contrast to the constraints of on-premises HPC. Every HPC configuration is potentially accessible to any given workload in a well-resourced cloud HPC deployment, with vast scalability to spin up as much compute as that workload demands in any given moment. Read more…

HPE Extreme Performance Solutions

Intel FPGAs: More Than Just an Accelerator Card

FPGA (Field Programmable Gate Array) acceleration cards are not new, as they’ve been commercially available since 1984. Typically, the emphasis around FPGAs has centered on the fact that they’re programmable accelerators, and that they can truly offer workload specific hardware acceleration solutions without requiring custom silicon. Read more…

IBM Accelerated Insights

Building a Solid IA for Your AI

The journey to high performance precision medicine starts with designing and deploying a solid Information Architecture that addresses the spectrum of challenges from data and applications that need to be managed and orchestrated together to empower workloads from analytics to AI. Read more…

IDAS: ‘Automagic’ HPC With Training Wheels

September 12, 2019

High-performance computing (HPC) for research is notorious for having steep barriers to entry. For this reason, high-tech disciplines were early adopters, have used the most cycles and typically drove hardware and softwa Read more…

By Elizabeth Leake

IDAS: ‘Automagic’ HPC With Training Wheels

September 12, 2019

High-performance computing (HPC) for research is notorious for having steep barriers to entry. For this reason, high-tech disciplines were early adopters, have Read more…

By Elizabeth Leake

Univa Brings Cloud Automation to Slurm Users with Navops Launch 2.0

September 11, 2019

Univa, the company behind Grid Engine, announced today its HPC cloud-automation platform NavOps Launch will support the popular open-source workload scheduler Slurm. With the release of NavOps Launch 2.0, “Slurm users will have access to the same cloud automation capabilities... Read more…

By Tiffany Trader

When Dense Matrix Representations Beat Sparse

September 9, 2019

In our world filled with unintended consequences, it turns out that saving memory space to help deal with GPU limitations, knowing it introduces performance pen Read more…

By James Reinders

Eyes on the Prize: TACC’s Frontera Quickly Ramps up Science Agenda

September 9, 2019

Announced a year ago and officially launched a week ago, the Texas Advanced Computing Center’s Frontera – now the fastest academic supercomputer (~25 petefl Read more…

By John Russell

Quantum Roundup: IBM Goes to School, Delft Tackles Networking, Rigetti Updates

September 5, 2019

IBM today announced a new open source quantum ‘textbook’, a series of quantum education videos, and plans to expand its nascent quantum hackathon program. L Read more…

By John Russell

DARPA Looks to Propel Parallelism

September 4, 2019

As Moore’s law runs out of steam, new programming approaches are being pursued with the goal of greater hardware performance with less coding. The Defense Advanced Projects Research Agency is launching a new programming effort aimed at leveraging the benefits of massive distributed parallelism with less sweat. Read more…

By George Leopold

Fastest Academic Supercomputer Enters Full Production at TACC, Just in Time for Hurricane Season

September 3, 2019

Frontera, the NSF supercomputer installed at the Texas Advanced Computing Center (TACC) in June, passed its formal acceptance last week and is now officially la Read more…

By Tiffany Trader

MIT Prepares for Satori…and a New 2 Petaflops Computer Too

August 27, 2019

Sometime this fall, MIT will fire up Satori – an $11.6 million compute cluster donated by IBM and coinciding with the opening of the MIT Stephen A. Schwarzma Read more…

By John Russell

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

DARPA Looks to Propel Parallelism

September 4, 2019

As Moore’s law runs out of steam, new programming approaches are being pursued with the goal of greater hardware performance with less coding. The Defense Advanced Projects Research Agency is launching a new programming effort aimed at leveraging the benefits of massive distributed parallelism with less sweat. Read more…

By George Leopold

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

A Behind-the-Scenes Look at the Hardware That Powered the Black Hole Image

June 24, 2019

Two months ago, the first-ever image of a black hole took the internet by storm. A team of scientists took years to produce and verify the striking image – an Read more…

By Oliver Peckham

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

Chinese Company Sugon Placed on US ‘Entity List’ After Strong Showing at International Supercomputing Conference

June 26, 2019

After more than a decade of advancing its supercomputing prowess, operating the world’s most powerful supercomputer from June 2013 to June 2018, China is keep Read more…

By Tiffany Trader

Qualcomm Invests in RISC-V Startup SiFive

June 7, 2019

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups. Last fall, Esperanto Technologies announced a $58 million funding round. Read more…

By George Leopold

Intel Confirms Retreat on Omni-Path

August 1, 2019

Intel Corp.’s plans to make a big splash in the network fabric market for linking HPC and other workloads has apparently belly-flopped. The chipmaker confirmed to us the outlines of an earlier report by the website CRN that it has jettisoned plans for a second-generation version of its Omni-Path interconnect... Read more…

By Staff report

Intel Debuts Pohoiki Beach, Its 8M Neuron Neuromorphic Development System

July 17, 2019

Neuromorphic computing has received less fanfare of late than quantum computing whose mystery has captured public attention and which seems to have generated mo Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This