Quantinuum Closes in on Breakeven Point in Quantum Error Correction

August 4, 2022

BROOMFIELD, Colo., Aug. 4, 2022 – Quantinuum researchers have hit a significant milestone by entangling logical qubits in a fault-tolerant circuit using real-time quantum error correction. The research, published in a new scientific paper that was released on August 3rd, is the first experimental comparison study of different quantum error correction codes in similar environments and presents a collection of several different experiments. These experiments include:

  1. The first demonstration of entangling gates between two logical qubits done in a fully fault-tolerant manner using real-time error correction
  2. The first demonstration of a logical entangling circuit that has higher fidelity than the corresponding physical circuit.

This milestone achievement is important because it marks the first time that logical qubits have been shown to outperform physical qubits — a critical step towards fault-tolerant quantum computers.

“Quantinuum’s trapped-ion quantum computing roadmap is designed around continuous upgrades, enabled our flexible architecture and our precision control capabilities. This combination provides for outstanding, first-of-its-kind achievements that help accelerate the entire industry,” said Tony Uttley, president and COO of Quantinuum.

David Hayes, a theory and architecture technical manager at Quantinuum and co-author of the new research paper, said the research moves quantum computing closer to the point where encoded circuits outperform more primitive operations.

“People have worked with error corrected qubits before, but they haven’t reached this sort of special point where the encoded operation is working better than the primitive operation,” Hayes said. “The other thing that’s new here is that in other experiments we’re doing the error correction while we’re doing the operations. An important next step for us is to get the error rate induced by the error correction itself down further.”

The findings are described in the new research paper, “Implementing Fault-tolerant Entangling Gates on the Five-Qubit code and the Color Code.”  The paper was recently published on the arXiv. Scientists used both the H1-1 and the H1-2 quantum computers, Powered by Honeywell, to compare the Five-Qubit error code and the Distance Three Color Code in these tests.

Quantum researchers are in the early days of experimental quantum error correction with a multitude of codes to test. Quantinuum researchers can explore a wider range of quantum error codes, compared to other quantum hardware designs, due to the architecture of the machine.

The System Model H1 uses a trapped-ion design and a quantum charged coupled device architecture (QCCD). Along with the inherent flexibility of this design, another strength is all-to-all connectivity. All the qubits are connected to each other which makes it easy to move information through chains of ions without creating multiple errors along the way.

“Instead of having to build a new machine every time we want to try a new code, we can just program the machine to run a different code, make the measurements and weigh the different pros and cons,” Hayes said.

Advancing Quantum Error Correction

All forms of technology need error correction including servers in data centers and space probes sending transmissions back to Earth. For Quantinuum and other companies in the quantum computing sector, quantum error correction is one of the most important pillars of progress. Errors prevent quantum computers from producing reliable results before they are overwhelmed. Quantinuum’s researchers are working toward the milestone of fault tolerance, meaning the errors can be suppressed to arbitrarily low levels.

Natalie Brown, another co-author of the paper and an advanced physicist at Quantinuum, said that most classical error correction principles fail with quantum computers because of the basic nature of quantum mechanics.

“It becomes very difficult to suppress noise to very small levels, and that becomes a problem in quantum computing,” she said. “The most promising candidate was this quantum error correction, where we take the physical qubits, make a logical qubit.”

Logical qubits are groups of physical qubits working together to perform a computation. For each physical qubit used in a computation, other ancillary qubits perform a range of tasks such as spotting and correcting errors as they occur.

Ciaran Ryan-Anderson, a senior advanced physicist at Quantinuum and also a co-author of the new paper, said the newest research paper builds on research performed in 2021 and published in Physical Review X. That work explained how researchers at Honeywell Quantum Solutions applied multiple rounds of quantum error correction to a single logical qubit.

“One of the first really important things to demonstrate was these repeated rounds of quantum error correction cycles,” he said.

That is one of several milestones on Ryan-Anderson’s quantum error correction checklist:

  1. Conduct repeated rounds of fault tolerant quantum error correction
  2. Feed forward and conditionally apply syndrome extraction
  3. Enable real-time determination of correction for a quantum error correction code
  4. Demonstrate general algorithmic real-time decoding
  5. Scale up quantum error correction with two logical qubits
  6. Hit the breakeven point when logical quantum computing starts to outperform physical quantum computing

“Quantinuum has achieved some of the milestones required to accomplish this now,” Ryan-Anderson said.

Five-Qubit Code vs. Color Code

Building upon the 2021 research involving one logical qubit, the newest research illustrates the Quantinuum team’s progress with quantum error correction and two logical qubits. The team tested two error codes familiar to quantum experts: the Five-Qubit Code and the Color Code. The Five-Qubit Code does not allow for a fault tolerant transversal gate using only two logical qubits. Researchers used “pieceable” fault tolerance to decompose an initially non-fault tolerant logical gate operation into pieces that are individually fault-tolerant. The Color Code, however, does allow the use of a transversal CNOT gate which is naturally fault-tolerant.

How the Experiment Worked

H1-2 can use up to 12 qubits and H1-1 can use up to 20. The Five-Qubit Code tested on H1-2 while the Color Code tested on H1-1. Both computers use the same surface electrode ion trap to control ytterbium ions as qubits. Ion transport to isolated gate zones with focused laser beams provides low crosstalk gate and mid-circuit measurement operations.

The researchers ran five experiments with different combinations of circuit elements to test the Five-Qubit Code and to understand the impact of fault tolerant design and circuit depth. The team found that the extra circuitry designed to increase fault tolerance had a negative impact on the overall fidelity of the logical operation, due to the large number of CNOT operations required.

The Color Code showed much better results due in part to the ability to use a transversal CNOT gate. The team ran seven experiments to investigate the fault tolerant potential of these codes. With the Color Code, the researchers found that the State Preparation and Measurement circuits benefitted from the addition of fault tolerant circuitry with a significant reduction of error rates: 99.94% for the logical qubits compared to 99.68% for the physical qubits. This was the only additional circuitry required to make the circuit fault tolerant from end-to-end, since the logical CNOT is transversal and naturally fault tolerant.

The researchers concluded that the “relatively economical fault tolerant circuitry of the Color Code will provide a better platform for computation than the qubit efficient five-qubit code.” Also, the researchers found that the Five-Qubit Code would be useful only in systems with far lower physical error rates than quantum computers have at this point in time.

Hayes said the team’s next step will be to surpass the breakeven point and provide proof of the work. “We are getting evidence that we’re really darn close to that point, but there’s a lot of work that needs to be done to actually prove it,” he said. “Just getting right there is not good enough, you have to actually get past it.”

A New Classical+Quantum Connection

Another advance from this experiment is a new classical processor with enhanced capabilities which will be essential to scalable algorithmic decoders. The data from the classical functions were used to dictate the control flow and operations executed in the quantum program.

The decoders used in these experiments were partially written in Rust and compiled to WebAssembly (Wasm).  The choice of Wasm provides an efficient, safe, and portable classical language to have functions that are callable from quantum programs.

The decoder implemented in Rust uses many high-level program constructs. The support for these features means that various scalable algorithmic decoders can be ergonomically implemented in various high-level languages that compile to Wasm (such as Rust, C, and C++) and called from quantum programs.

“It was pretty enabling for this particular experiment, and it’ll be even more important for future experiments as these things get more and more complicated,” Hayes said.

Another advantage of the trapped ion architecture is the ability to do real-time decision making during the execution of the quantum circuit thanks to long coherence times and the ability to do mid-circuit measurement and reset qubits as needed.

“Our systems have very long coherence times which is super advantageous when integrating in the classical compute real-time decision making,” Hayes said.

Source: Quantinuum

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

12 Midwestern Universities Team to Boost Semiconductor Supply Chain

August 8, 2022

The combined stressors of Covid-19 and the invasion of Ukraine have sent every major nation scrambling to reinforce its mission-critical supply chains — including and in particular the semiconductor supply chain. In th Read more…

Quantum Pioneer D-Wave Rings NYSE Bell, Begins Life as Public Company

August 8, 2022

D-Wave Systems, one of the early quantum computing pioneers, has completed its SPAC deal to go public. Its merger with DPCM Capital was completed last Friday, and today, D-Wave management rang the bell on the New York St Read more…

Supercomputer Models Explosives Critical for Nuclear Weapons

August 6, 2022

Lawrence Livermore National Laboratory (LLNL) is one of the laboratories that operates under the auspices of the National Nuclear Security Administration (NNSA), which manages the United States’ stockpile of nuclear we Read more…

SEA Changes: How EuroHPC Is Preparing for Exascale

August 5, 2022

Back in June, the EuroHPC Joint Undertaking — which serves as the EU’s concerted supercomputing play — announced its first exascale system: JUPITER, set to be installed by the Jülich Supercomputing Centre (FZJ) in 2023. But EuroHPC has been preparing for the exascale era for a much longer time: eight months before... Read more…

HPC Career Notes: August 2022 Edition

August 5, 2022

In this monthly feature, we’ll keep you up-to-date on the latest career developments for individuals in the high-performance computing community. Whether it’s a promotion, new company hire, or even an accolade, we’ Read more…

AWS Solution Channel

Shutterstock 1590905653

Expanded filesystems support in AWS ParallelCluster 3.2

Data is critical to HPC, and ensuring your simulations have the data they need — when they need it — is essential. However, data can originate from many sources and need to be consumed by diverse resources. Read more…

Microsoft/NVIDIA Solution Channel

Shutterstock 1731567844

Using Cloud-Based, GPU-Accelerated Systems for AML Fraud Detection

A major issue facing financial services organizations is tracking fraud due to money laundering. Trying to track money laundering is an expensive and time-consuming process due to the large volumes of financial data which must be analyzed. Read more…

Sniff Test: Supercomputer Research Investigates Odor Neutralizers

August 4, 2022

Factories, farms and landfills are functionally essential to our daily lives, but the less-than-desirable smells they often produce may be somewhat less necessary. Researchers from the University of New Orleans, the Louisiana Department of Environmental Quality, and the Jefferson Parish Department of Environmental Affairs in Jefferson, Louisiana... Read more…

SEA Changes: How EuroHPC Is Preparing for Exascale

August 5, 2022

Back in June, the EuroHPC Joint Undertaking — which serves as the EU’s concerted supercomputing play — announced its first exascale system: JUPITER, set to be installed by the Jülich Supercomputing Centre (FZJ) in 2023. But EuroHPC has been preparing for the exascale era for a much longer time: eight months before... Read more…

Not Just Cash for Chips – The New Chips and Science Act Boosts NSF, DOE, NIST

August 3, 2022

After two-plus years of contentious debate, several different names, and final passage by the House (243-187) and Senate (64-33) last week, the Chips and Science Act will soon become law. Besides the $54.2 billion provided to boost US-based chip manufacturing, the act reshapes US science policy in meaningful ways. NSF’s proposed budget... Read more…

CXL Brings Datacenter-sized Computing with 3.0 Standard, Thinks Ahead to 4.0

August 2, 2022

A new version of a standard backed by major cloud providers and chip companies could change the way some of the world's largest datacenters and fastest supercomputers are built. The CXL Consortium on Tuesday announced a new specification called CXL 3.0 – also known as Compute Express Link 3.0... Read more…

Inside an Ambitious Play to Shake Up HPC and the Texas Grid

August 2, 2022

With HPC demand ballooning and Moore’s law slowing down, modern supercomputers often undergo exhaustive efficiency efforts aimed at ameliorating exorbitant energy bills and correspondingly large carbon footprints. Others, meanwhile, are asking: is min-maxing the best option, or are there easier paths to reducing the bills and emissions of... Read more…

UCIe Consortium Incorporates, Nvidia and Alibaba Round Out Board

August 2, 2022

The Universal Chiplet Interconnect Express (UCIe) consortium is moving ahead with its effort to standardize a universal interconnect at the package level. The c Read more…

OpenCAPI to Be Folded into CXL

August 1, 2022

As the need for speed drives computational workloads, more standards organizations are coalescing around a standard called Compute Express Link – also known a Read more…

US CHIPS Act Close to Being Signed into Law

July 28, 2022

The U.S. House today passed the CHIPS and Science Act of 2022, which authorizes $280 billion in funding to boost semiconductor research and production in the country. The passage of the bill paves the way for U.S. president Joe Biden to sign the legislation into law, which would officially open up funding... Read more…

GE Research Enters the Exascale Era

July 28, 2022

The pitch for GE Research is easy, as Richard Arthur, senior director of computational methods research for GE Research, explained at the latest meeting of the DOE’s Advanced Scientific Computing Advisory Committee (ASCAC): a third of the electrons in the world that flow through devices are generated on GE equipment; every two seconds... Read more…

Nvidia R&D Chief on How AI is Improving Chip Design

April 18, 2022

Getting a glimpse into Nvidia’s R&D has become a regular feature of the spring GTC conference with Bill Dally, chief scientist and senior vice president of research, providing an overview of Nvidia’s R&D organization and a few details on current priorities. This year, Dally focused mostly on AI tools that Nvidia is both developing and using in-house to improve... Read more…

Royalty-free stock illustration ID: 1919750255

Intel Says UCIe to Outpace PCIe in Speed Race

May 11, 2022

Intel has shared more details on a new interconnect that is the foundation of the company’s long-term plan for x86, Arm and RISC-V architectures to co-exist in a single chip package. The semiconductor company is taking a modular approach to chip design with the option for customers to cram computing blocks such as CPUs, GPUs and AI accelerators inside a single chip package. Read more…

The Final Frontier: US Has Its First Exascale Supercomputer

May 30, 2022

In April 2018, the U.S. Department of Energy announced plans to procure a trio of exascale supercomputers at a total cost of up to $1.8 billion dollars. Over the ensuing four years, many announcements were made, many deadlines were missed, and a pandemic threw the world into disarray. Now, at long last, HPE and Oak Ridge National Laboratory (ORNL) have announced that the first of those... Read more…

US Senate Passes CHIPS Act Temperature Check, but Challenges Linger

July 19, 2022

The U.S. Senate on Tuesday passed a major hurdle that will open up close to $52 billion in grants for the semiconductor industry to boost manufacturing, supply chain and research and development. U.S. senators voted 64-34 in favor of advancing the CHIPS Act, which sets the stage for the final consideration... Read more…

Top500: Exascale Is Officially Here with Debut of Frontier

May 30, 2022

The 59th installment of the Top500 list, issued today from ISC 2022 in Hamburg, Germany, officially marks a new era in supercomputing with the debut of the first-ever exascale system on the list. Frontier, deployed at the Department of Energy’s Oak Ridge National Laboratory, achieved 1.102 exaflops in its fastest High Performance Linpack run, which was completed... Read more…

Newly-Observed Higgs Mode Holds Promise in Quantum Computing

June 8, 2022

The first-ever appearance of a previously undetectable quantum excitation known as the axial Higgs mode – exciting in its own right – also holds promise for developing and manipulating higher temperature quantum materials... Read more…

AMD’s MI300 APUs to Power Exascale El Capitan Supercomputer

June 21, 2022

Additional details of the architecture of the exascale El Capitan supercomputer were disclosed today by Lawrence Livermore National Laboratory’s (LLNL) Terri Read more…

PsiQuantum’s Path to 1 Million Qubits

April 21, 2022

PsiQuantum, founded in 2016 by four researchers with roots at Bristol University, Stanford University, and York University, is one of a few quantum computing startups that’s kept a moderately low PR profile. (That’s if you disregard the roughly $700 million in funding it has attracted.) The main reason is PsiQuantum has eschewed the clamorous public chase for... Read more…

Leading Solution Providers


ISC 2022 Booth Video Tours


Exclusive Inside Look at First US Exascale Supercomputer

July 1, 2022

HPCwire takes you inside the Frontier datacenter at DOE's Oak Ridge National Laboratory (ORNL) in Oak Ridge, Tenn., for an interview with Frontier Project Direc Read more…

AMD Opens Up Chip Design to the Outside for Custom Future

June 15, 2022

AMD is getting personal with chips as it sets sail to make products more to the liking of its customers. The chipmaker detailed a modular chip future in which customers can mix and match non-AMD processors in a custom chip package. "We are focused on making it easier to implement chips with more flexibility," said Mark Papermaster, chief technology officer at AMD during the analyst day meeting late last week. Read more…

Intel Reiterates Plans to Merge CPU, GPU High-performance Chip Roadmaps

May 31, 2022

Intel reiterated it is well on its way to merging its roadmap of high-performance CPUs and GPUs as it shifts over to newer manufacturing processes and packaging technologies in the coming years. The company is merging the CPU and GPU lineups into a chip (codenamed Falcon Shores) which Intel has dubbed an XPU. Falcon Shores... Read more…

Nvidia, Intel to Power Atos-Built MareNostrum 5 Supercomputer

June 16, 2022

The long-troubled, hotly anticipated MareNostrum 5 supercomputer finally has a vendor: Atos, which will be supplying a system that includes both Nvidia and Inte Read more…

India Launches Petascale ‘PARAM Ganga’ Supercomputer

March 8, 2022

Just a couple of weeks ago, the Indian government promised that it had five HPC systems in the final stages of installation and would launch nine new supercomputers this year. Now, it appears to be making good on that promise: the country’s National Supercomputing Mission (NSM) has announced the deployment of “PARAM Ganga” petascale supercomputer at Indian Institute of Technology (IIT)... Read more…

Is Time Running Out for Compromise on America COMPETES/USICA Act?

June 22, 2022

You may recall that efforts proposed in 2020 to remake the National Science Foundation (Endless Frontier Act) have since expanded and morphed into two gigantic bills, the America COMPETES Act in the U.S. House of Representatives and the U.S. Innovation and Competition Act in the U.S. Senate. So far, efforts to reconcile the two pieces of legislation have snagged and recent reports... Read more…

AMD Lines Up Alternate Chips as It Eyes a ‘Post-exaflops’ Future

June 10, 2022

Close to a decade ago, AMD was in turmoil. The company was playing second fiddle to Intel in PCs and datacenters, and its road to profitability hinged mostly on Read more…

Exascale Watch: Aurora Installation Underway, Now Open for Reservations

May 10, 2022

Installation has begun on the Aurora supercomputer, Rick Stevens (associate director of Argonne National Laboratory) revealed today during the Intel Vision event keynote taking place in Dallas, Texas, and online. Joining Intel exec Raja Koduri on stage, Stevens confirmed that the Aurora build is underway – a major development for a system that is projected to deliver more... Read more…

  • arrow
  • Click Here for More Headlines
  • arrow